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error after design import

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avg_emp

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hi all,

I'm new to cadence SoC 5.2 & using artisan 5.2 library.
After design import I get error as :-

==> ERROR: Cannot find 'clocks' that match 'clk pin' (File .constr.2578.pt, Line
9) <TCLCMD-917>.
==> ERROR: Can't get clock definition for clock '' (File .constr.2578.pt,
Line 9) <TCLCMD-265>.
Info: read_dc_script finished with 0 WARNING and 2 ERROR <USER-400>.

please detail how to remove it.
THANKS!!
 

nanda_kishore

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Hi ,

This is mostly because of the missing SDC or missing clk definition.. check in the dc script weather clk/clk name is defined or correctly mentioned or not and if defined check if clk frequency and clk period are correctly defined. If this is defined properly.. then it is the clear cut case of missing sdc/IO constraints.
 

vreddy

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Hi,

Just play around with .sdc file & change clk frequency & clk period.......& import again......if again it shows error let me know..

regards
vreddy
 

skymusic

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Maybe, you miss the clock defintion. Had better get the sdc constraint file from dc synthesis.
 

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