Error 10327 : Quartus 2 software..

[hangieok]

Hi! I have been stuck for awhile on my vhdl coding on quartus 2 software.. I cannot run the compilation since the error 10327 showed up.. I don't know what it's means.. Can someone explain to me why my coding is not working.. Tell me where it went wrong.. Thank you.. I appreciate the help and concern.. :-D

The coding:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity project_pwm is
PORT (
clk : IN STD_LOGIC; --system clock
data : IN STD_LOGIC_VECTOR; --8-bit input from muscle sensor through ADC
reset : IN STD_LOGIC; --synchronous reset
pwm : OUT STD_LOGIC); --pwm signal generated
end project_pwm;

architecture Behavioral of project_pwm is
constant upper :integer:=1000000; --indicates the upper boundary of the pwm in Hz
constant period:integer:=1000000;
constant dcycle_max :integer:=100000; --maximum value of pulse width
constant dcycle_min :integer:=50000; --minimum value of pulse width
constant duty_in : integer:=200;
signal pwm_reg, pwm_next:STD_LOGIC;
signal duty_cycle, duty_cycle_next: integer:=0;
signal counter, counter_next: integer:=0;
signal tick: STD_LOGIC; --Pulse width (Duty Cycle) is changed in period of PWM. so a variable called tick is defined.
--When tick is "1", duty cycle will change
begin
--register
process(clk,reset)
begin
if reset = '1' then
pwm_reg<='0';
counter<=0;
duty_cycle<=0;
elsif clk='1' and clk'event then
pwm_reg<=pwm_next;
counter<=counter_next;
duty_cycle<=duty_cycle_next;
end if;
end process;

counter_next<= 0 when counter = period else
counter+1;
tick<= '1' when counter= 0 else
'0';
--changing duty cycle
process (reset, data, clk)
begin
duty_cycle_next<=duty_cycle;
if tick ='1' then
if data='1' and duty_cycle>dcycle_min then
duty_cycle_next<=duty_cycle-duty_in;
elsif data='1'and duty_cycle<dcycle_max then
duty_cycle_next<=duty_cycle+duty_in;
end if;
end if;

 

[FvM]

Is it asking too much to expect the full error message quoted in your post?

I guess it's

can't determine definition of operator "="

Sounds reasonable because your are comparing a std_logic_vector with the std_logic literal '1'.