Equivalent ASIC and FPGA designs

[vibeguy]

So I have two questions, and these are kinda hefty so I apologize for that

Q1: If we use reprogrammable FPGAs to test implementations of IP, can an ASIC be designed and manufactured that looks almost identical; and vice versa: if we have an ASIC with known layout, is it possible to implement that in an FPGA with the same layout?
My thought is that the fixed logic blocks within an FPGA and routing through the switch matrices mean they will never be the same but I wonder if there's a way to get something close.

Q2: If we design a circuit implementation inside an FPGA, and only use a certain fraction of available blocks, how weakly are the unused blocks connected with the rest of the circuitry? For example, if power analysis is performed on the FPGA, how much will the unused parts of the chip affect the results?

Love to hear some thoughts!

 

[wwfeldman]

q1: yes
but i don't think its worth the time and the cost.
and, if something changes, you can re-program the FPGA
and throw out the ASIC

why would you want the ASIC to look like the FPGA?

q2: no idea
never worried about it
suggest you check with manufacturer

 

[vibeguy]

q1: yes
but i don't think its worth the time and the cost.
and, if something changes, you can re-program the FPGA
and throw out the ASIC

why would you want the ASIC to look like the FPGA?

Replicating an ASIC design on an FPGA is for testing purposes. ASIC are not cheap so testing certain methodologies on an FPGA to confirm the effectiveness is the goal. But whether or not the results would translate is the concern as some of the methodologies somewhat rely on hardware properties. A perfect clone isn't what I'm looking for, more trying to see if I can make some general conclusions based on findings from one of the implementations.

 

[HardwareBee]

There is something called ASIC Emulation Boards that help fabless emulate their ASIC design on a board based on FPGA before they go for tapeout. The main reason is because ASIC mask sets are very expensive and you can only produce them once (or more, but then you need to pay more). Therefore it's very normal for ASIC engineers to use FPGA chips to test their design (mostly their digital design).

But ASIC and FPGAs are fundamentally different, you can read here about FPGA vs ASIC:

FPGA vs ASIC, What to Choose? - AnySilicon

This is a high level article for those who are debating whether to use FPGAs or ASICs and need some technical and commercial insight to help ease the decision process. Both technologies, ASICs and FPGAs are absolutely fantastic and have great benefits but it’s up to you to figure out, based on...

anysilicon.com

FPGA vs ASIC - What is the Difference? (free calculator) - HardwareBee

In this article, we will take a look at the features which distinguish FPGA from ASIC and subsequently, what applications and situations these characteristics make either of the two ideal for. Both FPGA and ASIC are known technologies that have been around for several decades. Many electronic...

hardwarebee.com

Hope it helps,
Alex.

 

[HardwareBee]

So I have two questions, and these are kinda hefty so I apologize for that

Q1: If we use reprogrammable FPGAs to test implementations of IP, can an ASIC be designed and manufactured that looks almost identical; and vice versa: if we have an ASIC with known layout, is it possible to implement that in an FPGA with the same layout?
My thought is that the fixed logic blocks within an FPGA and routing through the switch matrices mean they will never be the same but I wonder if there's a way to get something close.

Q2: If we design a circuit implementation inside an FPGA, and only use a certain fraction of available blocks, how weakly are the unused blocks connected with the rest of the circuitry? For example, if power analysis is performed on the FPGA, how much will the unused parts of the chip affect the results?

Love to hear some thoughts!

Maybe this article would help you: https://anysilicon.com/fpga-vs-asic-choose/