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Equivalence checking (SPICE and a behavioral model)

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raghavkmr

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Equivalence checking(SPICE and behavioral model )

I have been doing equivalence checking between spice and behavioral model of an IP,
I am trying to verify the timings of both ,as behavioral is written in verilog the timescale is ns and my checker works perfectly ,but when it comes to spice the simulator shows same time but my checker is not working correctly,i inferred that i dont understand the output time scale of spice


like (clk_period >=139 && clk_period <=145)
verilog model works perfect
spice output is checked incorrect

what is time unit for spice output ??????????????
 

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