entity with Fixed point transformed into std_logic_vector in testbensh

[blach100]

Hello,
in My entity I have
*entity jasmin is*
*port (CLK, Reset : in std_logic;*

*xt, yt : out ufixed(0 downto -14));*
*end jasmin;*

*
when creating the Testbensh, It automatically giving me

* COMPONENT jasmin*
* PORT(*
* CLK : IN std_logic;*
* Reset : IN std_logic;*
* xt : OUT std_logic_vector(0 downto -14);*
* yt : OUT std_logic_vector(0 downto -14)*
* );*
* END COMPONENT;*

*

*
and when simulating using Modelsim (Student version)
*
*

*Error: testB1.vhd(46): (vcom-1144) Value -14 (of type std.STANDARD.NATURAL) is out of range 0 to 2147483647.

Do you have any Idea to solve this out!
thank you in advance
*

 

[barry]

You can't use a negative number (-14) as an index. Not sure why you would even want to do that.

 

[blach100]

i'm using negative number (-14) because the result of my module is actually numbers between 0 and 1

 

[barry]

i'm using negative number (-14) because the result of my module is actually numbers between 0 and 1

That makes absolutely no sense.

 

[blach100]

ok a brief introduction to my project
I would like to create a half sinewave, so the result of all the calculation must be between 0 and 1
I hope it makes sense now

 

[barry]

ok a brief introduction to my project
I would like to create a half sinewave, so the result of all the calculation must be between 0 and 1
I hope it makes sense now

Nope.

You still don't explain why you have a std_logic_vector with a negative index (which you can't have even if you DID explain it).

Why a negative index?

1) You just can't have a negative number for the index. Sorry.
2) You can't have a number "between 0 and 1" with a std_logic_vector.

 

[blach100]

yes I agree Mr barry,
if you see my entity in the module I have the output as fixed point number "ufixed"
my question now is, why when I created the testbensh using xilinx wizard, the type of the the output has transformed into std_logic_vector !!??
do you have any idea about it?

 

[barry]

do you have all the appropriate libraries declared? I don't believe the fixed package is actually a "standard" package. There may be some incompatibility with Microsim.Have you tried synthesizing the project, that might give some clues? Have you looked at the warnings from Microsim? How did you generate your testbench? You say it magically transformed your ufixed to std_logic_vector-there may be some messages from the testbench generator that explain the issue. Maybe you can edit your testbench so that it uses ufixed instead of slv.

- - - Updated - - -

do you have all the appropriate libraries declared? I don't believe the fixed package is actually a "standard" package. There may be some incompatibility with Microsim.Have you tried synthesizing the project, that might give some clues? Have you looked at the warnings from Microsim? How did you generate your testbench? You say it magically transformed your ufixed to std_logic_vector-there may be some messages from the testbench generator that explain the issue. Maybe you can edit your testbench so that it uses ufixed instead of slv.

 

[TrickyDicky]

Yes it does. Barry - ufixed and sfixed are part of the VHDL 2008 standard and they use -ve index to represent fractional parts of a fixed point number and +ve indexes for the integer. It makes perfect sense and works really well compared to using numeric_std where you have to keep track of your integer fractional separation with constants that keep changing depending on how many fractional bits you have.

Anyway, a proper answer to the OP - It looks like the testbench you have has been generated with some form of code generation? the problem with your code is that the component now does not match the entity. The problem is std_logic_vector only accepts natural ranges (ie 0 to 2^31-1) and not -ve indices. Looks like this code generation is pretty poor and insists you use std_logic_vectors (it must be a pretty poor generation tool).

I suggest trying to write the TB yourself to get around these silly errors.

Edit - noticed you used the Xilinx tool to generate the testbench - if you want to use ufixed you'll have to write the testbench yourself.

- - - Updated - - -

Yes it does. Barry - ufixed and sfixed are part of the VHDL 2008 standard and they use -ve index to represent fractional parts of a fixed point number and +ve indexes for the integer. It makes perfect sense and works really well compared to using numeric_std where you have to keep track of your integer fractional separation with constants that keep changing depending on how many fractional bits you have.

Anyway, a proper answer to the OP - It looks like the testbench you have has been generated with some form of code generation? the problem with your code is that the component now does not match the entity. The problem is std_logic_vector only accepts natural ranges (ie 0 to 2^31-1) and not -ve indices. Looks like this code generation is pretty poor and insists you use std_logic_vectors (it must be a pretty poor generation tool).

I suggest trying to write the TB yourself to get around these silly errors.

Edit - noticed you used the Xilinx tool to generate the testbench - if you want to use ufixed you'll have to write the testbench yourself.

 

[blach100]

all the appropriate libraries are declared,
in synthesising it gives me three warning in the Fixed point package; "me too I think it's not standard package",
i'm working with xilinx,
I generated the testbensh like the following : Right click on the module -> New source -> VHDL testbensh
I tried to edit my testbensh from std_logic_vector to ufixed, give me error : Error: testB3.vhd(46): (vcom-1136) Unknown identifier "ufixed".
!!!

 

[FvM]

I tried to edit my testbensh from std_logic_vector to ufixed, give me error : Error: testB3.vhd(46): (vcom-1136) Unknown identifier "ufixed".

I guess you forgot to import the fixed point libraries to the testbench. By the way, I think it would be appropriate to file a support request about this code generator limitation.

 

[blach100]

hey FvM, I always do the hard and forget about simple things like that,
your suggestion helped me dude;
thanks

and thanks to barry, TrickyDicky.

 

[barry]

Okay, I've learned something new today(haven't used the fixed-point package). But the main issue was that the testbench had a negative index for a std_logic_vector which expects only positive indices. As noted, there is apparently some problem with the Xilinx testbench generator.

 

[blach100]

i'm actually getting an earlier version of Xilinx to test the Testbensh generation
and I'll share the result.
best regard

- - - Updated - - -

the problem of the testbensh has been solved,
but I think this time it's a package error that rise up
this is the error while simulation.
: Error: fixed_pkg: Unbounded number passed, was a literal used?

 

[blach100]

I tried some other versions, 12,13,and my actual version of Xilinx ISE which is 14.1,
they all have the same "malfunctioning" on the generation of the Testbensh file.
they all transform the "Ufixed" to "std_logic_vector".

anyway, I have another problem after importing the fixed-point package to my testbensh this is the error while simulation.
: Error: fixed_pkg: Unbounded number passed, was a literal used?
do you guys have some idea ?

 

[TrickyDicky]

did you download the Xilinx version of the fixed_point package? the xilinx tools are pretty rubbish at VHDL.

 

[blach100]

I downloaded the xilinx packge from **broken link removed**