Encrypted Verilog File -> how does it looks like?

[ivlsi]

Hello All,

How does an Encrypted Verilog File look like? Is this an ASCII file?

As for the Synthesis tools, can they work with encrypted RTL?

Thank you!

 

[dave_59]

Yes, encrypted Verilog files are ASCII. Unless the tool supports a standard encryption mechanism like IEEE P1735, the Verilog source must be specifically encrypted for each tool that will need to read it.

 

[ivlsi]

What tools do currently support the standard encryption mechanism? Synopsys? Cadence? Mentor Graphics? etc? Is it not yet an industry standard?

 

[dave_59]

Modelsim/Questa supports it. I believe Xilinx supports it as well.

 

[ivlsi]

When I encrypt my code, I do it with some key-word. Should I give this key-word to someone who receive this encrypted code so that he/she would be able to simulate or synthesize it?
If I don't need to provide such key-word, how tools are able to understand the encrypted code?

 

[dave_59]

It depends on the encryption mechanism used by the tools you have. Public Key Encryption is a one-way encryption meaning that you use one key (public) to encrypt, and another key (private) to decrypt. That private key is only known by the tool vendor.

The IEEE P1735 standard is tied to a licensing mechanism that controls what the tool is able to do with an encrypted model. You might be able to encrypt a model so that anyone can simulate it, but not synthesize it.