Encounter power planning

[jelydonut]

Is there any decient documents or sites out there which explain proper concepts for rings, stripes, etc.. Im having trouble even finding out which widths i should use for these.

jelydonut

 

[tarkyss]

you can reference the techfile provided by foundry

 

[tony_taoyh]

For the width of ring, you can check the two info first:

(1) what is the max current in your IC?

(2) What is max current density of the metal from your foundry?


Then, you can make decision.

Of course, you need add some margin.
Usually, two times margin can apply.

 

[zhustudio]

That is true. For power planning, you must know your process spec. The max current per 1um. Always for TSMC 180nm is 1mA. But you need to leave margin. You can estimate power in netlist level simulation. Then , calculate the average and peak power.

For power connecting, different people have different style. Some one prefer large width of power strapes, 10-20um (power trunk), someone like use power mesh (both in vertical and horizontal).

You can use power analysis tools, such as AstroRail or Voltagestorm to check the static power. The main subject is IR Drop and EM. If your design is below 130nm, you must run dynamic power analysis. The test vector is got from your ATPG (the power during capture in ATPG testing is the peak power)

For more detail, you can view the help in EDA tools.
Power Compiler, Primepower, AstroRail, VoltageStorm.