Thank you for your replies.
It's straightforward for a counter, and i can not refear to any datasheet because i'm implementing a fsm in vhdl so i'd like to know the differences between the two signals in order to implement the correct one. For sure reset is mandatory, but what about enable? Could be usefull for the layout of the ic?
RESET pin is used to reset flip-flops in gate-level-netlist otherwise flip-flop goes in undefined state in ASIC ICs .
ENABLE is used to select chip, it is generally used by proper addressing of address buses to select IC.
this is misleading. reset is a reset, enable is an enable. both will be present in pretty much all code that you write.
it has nothing to do with whether you are doing gate level simulation or building asics or 'selecting chip'.
it is not for all designs.
i do not like to misleading anyone.
i have share my own experience concerned with ASIC IC design.
I have designed a small design of UART in that initially i had not used RESET pin then in post synthesis simulation problem came as all outputs were stuck at undefined state.
after using RESET it started work.
I have designed a small design of UART in that initially i had not used RESET pin then in post synthesis simulation problem came as all outputs were stuck at undefined state.
Hi,
isn´t there a defined state after power up for a real circuit?
Or is this only a simulation problem?
Klaus
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