Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Emulated DDR flip flop

Status
Not open for further replies.

shaiko

Advanced Member level 5
Joined
Aug 20, 2011
Messages
2,644
Helped
303
Reputation
608
Reaction score
297
Trophy points
1,363
Activity points
18,302
Code:
process ( clock ) is
  begin
    if rising_edge ( clock ) then
       Q1 <= D ;
    end if ;
  end process ;

process ( clock ) is
  begin
    if fallng_edge ( clock ) then
       Q2 <= D ;
    end if ;
  end process ;
   
Q_DDR <= Q1 or Q2 ;

1.Any reason for the above not to work in an FPGA ?
2.Is there a syntax to describe a VHDL DDR flip flop ?

For example, I know that the following won't work :

Code:
if rising_edge ( clock ) or falling_edge ( clock ) then
   Q_DDR <= D ;
end if ;

neither wil

Code:
if rising_edge ( clock ) then
   Q_DDR <= D ;
elsif falling_edge ( clock ) then
   Q_DDR <= D ;
end if ;

But why ?
Both of the above describe the behavioral model of a DDR flip flop.
 

But why ?
Both of the above describe the behavioral model of a DDR flip flop.

VHDL and Verilog are simulation languages. It is easy to write code that is impossible or difficult to synthesize. Your examples are difficult. Try to draw a schematic manually, using normal gates and flip-flops. You will probably understand why the tool can't do it.

I know that such flip-flops are available in some technologies, but I don't know if your examples will compile. The tool may require that the code is written in a special way.
 
  • Like
Reactions: shaiko

    shaiko

    Points: 2
    Helpful Answer Positive Rating
Its going to depend on the technology. Afaik, All FPGAs from the main vendors are single edge triggered only (accross the entire chip), with maybe some DDR ffs in hard cores that require them. If you were compiling for an ASIC, the code would be perfectly fine.

The only way to get a DDR FF in an FPGA is to run a clock at 2x main clock speed.
 
  • Like
Reactions: shaiko

    shaiko

    Points: 2
    Helpful Answer Positive Rating
The correct behavioral desription of the DDR output registers availble in recent FPGAs involves a multiplexer, not an OR gate. For bidirectional DDR pins, a respective OE control has to be added.

Its going to depend on the technology. Afaik, All FPGAs from the main vendors are single edge triggered only (accross the entire chip), with maybe some DDR ffs in hard cores that require them. If you were compiling for an ASIC, the code would be perfectly fine.

The only way to get a DDR FF in an FPGA is to run a clock at 2x main clock speed.

Besides reasonability considerations, it's always possible to have FFs clocked on different edges in a design. It's also possible to implement an "emulated" DDR FF block. The interesting question is about the required output timing, acceptance of glitches etc.
 
  • Like
Reactions: shaiko

    shaiko

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top