empty design error in ISE Mapping

[daryoosh23]

Hi,
I have the following famous error in ISE13.2 when I'm trying to implement my code:
ERROR:Map:116 - The design is empty. No processing will be done.
ERROR:Map:52 - Problem encountered processing RPMs.

Some people say it is because of lack of IOBs. Some others say it is because of an error in your vhdl code which cause removal of all the code by ISE. I checked my code and I rweally couldn't find any thing. Can any body help me? This is my vhdl code:

use work.mypackage.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VComponents.all;

entity mux1 is
Port ( input: in Mem(7 downto 0); mux1_c: in std_logic_vector(2 downto 0); output: out std_logic_vector (7 downto 0));
end mux1;

architecture Behavioral of mux1 is

begin

output <= input(to_integer(unsigned(mux1_c)));
end Behavioral;
-----------------------------------------------------------------------------------
use work.mypackage.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VComponents.all;

entity mux2 is
Port ( input: in Mem(3 downto 0); mux2_c: in std_logic_vector(1 downto 0); output: out std_logic_vector (7 downto 0));
end mux2;

architecture Behavioral of mux2 is

begin

output <= input(to_integer(unsigned(mux2_c)));
end Behavioral;
-----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
use work.mypackage.all;

entity SDA is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC );
end SDA;

architecture Behavioral of SDA is
component mux1 is port ( input: in Mem(7 downto 0); mux1_c: in std_logic_vector(2 downto 0); output: out std_logic_vector (7 downto 0)); end component;
component mux2 is port ( input: in Mem(3 downto 0); mux2_c: in std_logic_vector(3 downto 0); output: out std_logic_vector (7 downto 0)); end component;
constant L:integer :=7;
constant N:integer :=7;
signal S0: Mem(3 downto 0):=("10101010","01010101","10101010","10101010");
signal S1: Mem(3 downto 0):=("10101010","01010101","10101010","10101010");
signal E0: Mem(N downto 0):=("01101010","01010101","00101010","00111010","01101010","01010101","00101010","00111010");
signal E1: Mem(N downto 0):=("01101010","01010101","00101010","00111010","01101010","01010101","00101010","00111010");
signal R: Mem(7 downto 0):=("10101010","01010101","10101010","01010101","10101010","01010101","10101010","01010101");
signal R1: Mem(3 downto 0):=(others=>(others=>'0'));
signal mx1i: Mem(7 downto 0):=(others=>(others=>'0'));
signal mx2i: Mem(7 downto 0):=(others=>(others=>'0'));
signal cnt: std_logic_vector(1 downto 0);
signal cnt2: std_logic_vector(2 downto 0);
signal C1,e: std_logic:='0';
signal m1i1,m1_o,m2_o,DX1_I,DX1_o1,DX1_o2,MX1_o,MX2_o,mx3_o,mx4_o,mx5_o,mx6_o,MX7_o,reg,alpha : std_logic_vector(7 downto 0):="00000000";
signal T0:std_logic_vector(7 downto 0):="00000001";
signal T1:std_logic_vector(7 downto 0):="00000001";
signal a3_o,m1_temp,m2_temp : std_logic_vector(15 downto 0);
begin

M1I1 <= std_logic_vector( unsigned(MX1_o) + unsigned(MX2_o));
m1_temp <= std_logic_vector( unsigned(m1i1) * unsigned(S1(3)));
m1_o <= m1_temp (15 downto 8);
MX2i(0) <= "00000000";
MX2i (L downto 1) <= R( L downto 1);
m2_temp <= std_logic_vector( unsigned(alpha) * unsigned(MX7_o));
m2_o <= m2_temp (15 downto 8);
DX1_I <= std_logic_vector( unsigned(m2_o) + unsigned(A3_o));
A3_o <= std_logic_vector( unsigned(MX4_o) + unsigned(MX5_o));
MX5_o <= MX3_o WHEN e='0' ELSE
E1(1);
MX4_o <= reg WHEN e='0' ELSE
E1(0);
MX7_o <= mx6_o WHEN e='0' ELSE
E0(0);

process(DX1_I,e)
begin
case e is
when '0' => DX1_o1 <= DX1_I; DX1_o2 <= "ZZZZZZZZ";
when '1' => DX1_o1 <= "ZZZZZZZZ"; DX1_o2 <= DX1_I;
WHEN OTHERS => DX1_o1 <= "ZZZZZZZZ"; DX1_o2 <= "ZZZZZZZZ";

end case;
end process;

process(clk)
begin
if (clk'event and clk='1') then
if (c1='0' and e='0') then
T1 <= std_logic_vector( unsigned(m1_o) + unsigned( T1));
cnt <= std_logic_vector( unsigned(cnt) + 1);
reg <= Mx3_o;
S1(3) <=Dx1_o1;
S1(2 downto 0) <=s1(3 downto 1);
S0(3)<= MX4_o;
S0(2 downto 0) <= S0(3 downto 1);
if (cnt="11") then
c1 <='1';
cnt2 <= "000";
end if;
elsif (c1='1' and e='0') then
alpha <= std_logic_vector( unsigned(T1) * unsigned(T0));
T0 <=T1;
T1<="00000000";
e <= '1';
elsif (c1='1' and e='1') then
cnt2 <= std_logic_vector( unsigned(cnt2) + 1);
E1(N) <= Dx1_o2;
E0(N) <= E1(0);
if (cnt2 = "111") then
e <='0';
c1 <= '0';
cnt <= "00";
end if;
end if;
end if;
end process;
R1<=R(3 downto 0);
-- mx1: mux2 port map (R1 ,cnt, MX1_o);
MX1_o <= R1(to_integer(unsigned(cnt)));
-- mx2: mux1 port map (MX2i,cnt2, mx2_o);
MX2_o <= MX2i(to_integer(unsigned(cnt2)));
-- mx3: mux2 port map (S1,cnt, mx3_o);
MX3_o <= S1(to_integer(unsigned(cnt)));
-- mx6: mux2 port map (S0,cnt, mx6_o);
MX6_o <= S0(to_integer(unsigned(cnt)));
end Behavioral;

 

[barry]

It looks to me like your top level is SDA, and it's only got 2 inputs, and that's it. What you've described is a VHDL paperweight.

Further, you've instantiated your two MUX components, and then commented them out!! It's not clear WHAT you're trying to do here.

 

[TrickyDicky]

The problem is SDA has no outputs. If theres no output, then theres no point having any logic, because the design does nothing.

 

[daryoosh23]

My plan was to just have reults, E1(i), as values in the internal memories(registers) and have an estimation for power and area and speed. However it seems that I have to define them as output port. This architecture is a part of larger architecture and just calculate E1(i) and then based on the values of E(i) a decision will be taken in top level architecture. I mean this part doesn't use any IO buffer or phisical pin. I should find another way to estimate A/P/S of my architecture.
Anyway thanks for your help.

 

[TrickyDicky]

If you planned to store these values internally, how did you expect to read them? Its a bit like a WOM :https://en.wikipedia.org/wiki/Write-only_memory_(joke)