embeded chip from RTL to GDSII, synthesis

[linuxluo]

Hi, All
Now I am design a embeded chip from RTL to GDSII. My tools are VCS,DC,PT,SE,assura.
Can some guys tell me how to synthesis these tools in design flow in detail ? Especially in backend floorplan and route.
p.s. I am able to use tools.

 

[philewar]

Re: asic design flow help

Hi, All
Now I am design a embeded chip from RTL to GDSII. My tools are VCS,DC,PT,SE,assura.
Can some guys tell me how to synthesis these tools in design flow in detail ? Especially in backend floorplan and route.
p.s. I am able to use tools.

coding in verilog, vcs to simulate, dc to synthesis, pt to sta, vcs to re-simulate, se to p&r, pt to do sta, vcs to post-simulate, assura to drc and lvs

then sign-off!

 

[ntxp]

how about mixed signal chip design flow? especially on soc design..

ntxp

 

[philewar]

SOC is a big story, and I have to admit I'm not clear about it.
May some experts answer the question.

 

[bravobravo]

asic design flow help

1 . use ECS or cohesion for Soc design, we adopt this ...
many of my friend do this ..
2. use cohesion to generate analog spice and digital hdl gate level netlist ..
(if your digital block have spice netlist , it will do also .)

3. then use nanosim to simulate analog block using spice mode , digital using vcs tools..(the tools will communication each other ..)

hope this answer will help you more ....

 

[yasonwang]

floorplan

FE or floorplan manager to do floorplan; IE to place block; SE to P&R;
Voltagestorm or Arcadia to analyze power rail; Celtic to analyze crosstalk and electromigation;