Emacs verilog mode: AUTOINOUT challenge

[viv_1005]

emacs autoreg

Hello!
I have following challenge.

module x(/*AUTOARG*/);

/*AUTOINOUT*/
/*AUTOWIRE*/
/*AUTOREG*/

wire [32:0] a;
assign a = b0? a0: b1?a1 : b2?a2;

my_module u0_my_module(/*AUTOINST*/
.a(a0),
.b(b0));

my_module u1_my_module(/*AUTOINST*/
.a(a1),
.b(b1));

my_module u2_my_module(/*AUTOINST*/
.a(a2),
.b(b2));

endmodule

After writing this, if I do a ctrl-C ctrl-A, I get b0, b1, b2 in the IO list. whereas I want only a in the IOs. Can you suggest me where am I going wrong

 

[wkong_zhu]

emacs verilog-mode autoinst

you can't use AUTOINOUT in such case.
I recommend use AUTOARG AUTOINST AS.
Don't use others to prohibit errors.