efficient way to add increment a std_logic_vector

[manasic]

Hello all;

I am writing a code for FIFO buffer and come across a stage in which I need to increment my read and write pointer. The read and write pointer are std_logic_vector. So incrementing it by 1; requires a hell lot of type cast conversion. It looks something like this:

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Code VHDL - [expand]
1
std_logic_vector(to_unsigned(((to_integer(unsigned(weptr))) + 1),4))

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I am very newbie to VHDL, can anyone suggest a better and efficient way to do this.

Thanks and regards;
Manasi.:roll:

 

[barry]

Use the unsigned library (std_logic_unsigned). You will then be able to perform arithmetic on std_logic_vectors, e.g., a<=b+c;

 

[permute]

In many case, you can also use either unsigned or integer (range 0 to N-1) types.

If you feel bad about using std_logic_unsigned, you can also write your own wrapper functions for "+"(x,y : std_logic_vector) and others.

At a minimum, unsigned + integer is defined, so you can do std_logic_vector(unsigned(weptr)+1).

 

[manasic]

thanks all, I understood ..

 

[std_match]

I would use the numeric_std library and declare the pointers as "unsigned".
For hobby projects you can use any library, but as a professional you can expect that the non-standard libraries std_logic_unsigned, std_logic_arith etc. can be forbidden by some customers/employers. Therefore, if you are learning VHDL I recommend that you only use numeric_std.

 

[BlackHelicopter]

I would use the numeric_std library and declare the pointers as "unsigned".
For hobby projects you can use any library, but as a professional you can expect that the non-standard libraries std_logic_unsigned, std_logic_arith etc. can be forbidden by some customers/employers. Therefore, if you are learning VHDL I recommend that you only use numeric_std.

I've seen both numeric_std and std_logic_unsigned used by professionals. Although not 'proper coding', std_logic_unsigned still gets used and adding directly to a std_logic_vector does look cleaner to me I have to say.

 

[barry]

I'm a professional, and I use std_logic_unsigned. But I don't use std_logic_arith.

 

[TrickyDicky]

I'm a professional, and I use std_logic_unsigned. But I don't use std_logic_arith.

It depends on what the company coding guidelines are. Many companies dont really care what you do as long as it works and ships on time. But some will.

 

[std_match]

My point is that numeric_std is the safe way to go. It is a fact that std_logic_arith, std_logic_unsigned etc are forbidden in some projects/companies. I expect numeric_std to be allowed everywhere.

To the OP: it is not necessary to go all the way to integer if you really want to increment a std_logic_vector using numeric_std. It is enough to go to unsigned:

weptr <= std_logic_vector(unsigned(weptr) + 1);

Edit:
I see that this way of incrementing has already been mentioned by permute in post #3