Effect of Process Variations on Clock Skew

[alekya.mohan]

effect of process skew on chips

How I mathematically model the effect of Process Variations on Clock Skew?
Process Variaitons in the sense: Gate Length, Width, Channel Length doping etc..
Could you please suggest me any books where from I can get atleast a clue regarding this topic?

 

[entropy]

chip level spice netlist simulation...an overwhelming job... in digital world, we have set_clock_uncertainty to model this value.

 

[Colbhaidh]

For a foundry process, you will have been given the Spice model for the target (normal) process and models for Fast and slow nmos and pmos.
You should run simulations for all variations e.g.
nmos pmos
N N
F N
N F
S N
N S
F F
F S
S S
etc, etc