dathoang86
Newbie level 5
Please help me. I design a ADC circuit at 160 MSPS clock.
My circuit will operate in a high electron-magnetic, there are much noise in this envirment. I wonder about data trace layout, can i need to layout it in inner layer( in layers under top layer) ?
My circuit will operate in a high electron-magnetic, there are much noise in this envirment. I wonder about data trace layout, can i need to layout it in inner layer( in layers under top layer) ?