Effect of doubling via cuts on the parasitics

[Abdo18]

If I doubled the number of all via cuts in my design, how could this affect the resistance and capacitance, thus I know how it affects timing?

 

[k_90]

the resistance would be reduced, capacitance increased but your not looking at large amounts. Better for DRM (design for manufacturing) I doubt it would affect timing but might make routing more congested.

 

[dick_freebird]

If via resistance dominates (as could be the case
with tungsten plug and aluminum metallization)
then you halve that component of net resistance.

Doublets also can drive up yield and reliability if
the fab has marginal control of via integrity, to
the what, 99.9999% degree (for a 1M via chip,
which is not outside reason today). Turn a 10%
yield detractor into a 1% (assuming no other
issues relating to lonely vs doublet via litho).

 

[ThisIsNotSam]

If I doubled the number of all via cuts in my design, how could this affect the resistance and capacitance, thus I know how it affects timing?

it's worth pointing out that the paths that are really critical will be routed with M1/M2 mostly, thus the number of vias is minimal. timing is, in theory, affected, but it's not like the standard cells allow for dual vias to land on them. you will actually only see benefits on M2/M3 and above, which are not that important.

 

[timof]

It depends on the layout and operating conditions.

Sometimes, a single via will be limiting your resistance, voltage drop, or RC delay - in which case, you want to double (or quadruple) the number of vias.

If via contribution is small, then it does not make sense to double it (unless this improves the yield) - it may increase parasitic capacitance.

Proper EDA tools will tel you how critical this or that via or group of vias is, for your characteristic of interest.

This may be especially important for optimizing low-capacitance nets, like pads for high-speed signals, to minimize net capacitance (ESD diodes plus parasitics), without affecting resistance and current density for ESD.