Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Effect of delay on PLL bandwidth

Not open for further replies.


Member level 3
Aug 26, 2015
Reaction score
Trophy points
Activity points
Hi everyone,

The PLL bandwidth is proportilanl to the charge pump current (Icp), the Kvco and the divider ratio N.

But if were to add a delay block to the PLL the would the bandwidth change? How do I get an equation that incorporates the delay in the bandwidth?

Delay would mean equivalently adding one or more poles.If the pole is closer to the old BW,yeah the BW may change ,if the delay is very small,it wouldn't effect it significantly.
I think this would answer your second question also.
Hope it helps.
Why do you have delay in the system?
Because of the capacitors,the voltage across them cannot change instantaneously,they take time to charge up.

In practice, extra delay means that you need to slow down the rate of correction to prevent excessive overshoot and potential instability.
This has the effect of reducing the bandwidth.

The effect of extra delay is similar to greatly increasing "N" because it takes a finite time for a change at the VCO to ripple through the N counter to the phase detector.


A delay generates a phase shift.
While the delay is constant, the amount (in degree) of phase shift depend on frequency.

Imagine a delay of 1us.
With a 100k Hz signal a full wave (360°) takes 10us. So 1us equals to 36° phase shift.
With a 10 kHz signal the same delay equals to 3.6° phase shift
With a 1MHz signal the delay equals to 360° phase shift.

Delay within a regulation loop is often problematic for stability.

To stabilise a regulation loop with considerable delay time often needs to attenuate feedback signal, but this makes a regulation loop unprecise and slow. Best is to keep delay times low - but at least constant. It should not vary with time, temperature, supply voltage...


A delay generates a phase shift.

Ok I understood that now.

Now, for the PLL. The output of the phase frequency detector (PFD) is a phase shift between the input and output signals. Let that be phase shift be (phi)
If I were to add a delay element after the PFD, could I say that (phi) is now changed to (phi) + (phi-d) ? (phi-d) is now the phase shift caused by the delay element.

- - - Updated - - -

Continued from the previous post

And changing that delay would influence the closed loop bandwidth?


i think both is correct.


Not open for further replies.

Part and Inventory Search

Welcome to