EEPROM writes atomic?

[supercat]

When using a serial EEPROM, under what circumstances may EEPROM page-writes be assumed to be atomic (e.g. if a system disruption occurs around the time of a page write, either the entire write will succeed, or no data will be disturbed) and what safeguards are required to ensure that they will be?

If an EEPROM chip were to lose power during a page-write, I would expect that some chips would be guaranteed to behave as though all bits that were "0" would be erased in random sequence and then all bits which were supposed to be "0" would be programmed in random sequence. On some other chips, all bits would be programmed to "0" in random sequence, then all bits erased in random sequence, and then selected bits programmed. In the latter case, any combination of bits could occur as a result of a power-interrupted program operation. Since manufacturers don't specify either behavior, it would seem the safe course of action would be to ensure that an EEPROM has enough capacitance on its power supply to handle the energy required for a write. Can the amount of charge required ever be anything close to the maximum write current times the maximum write duration, or is the maximum current only required when precharging some circuitry? Adding a 47uF cap seems a little extreme.

Also, what techniques are most practical for ensuring that a host processor reset won't cause an inadvertent partial-page write? On an I2C part, if one could ensure that a reset would not cause SDA to float high while SCK was high, one could prevent a write by having one's reset routine float SDA while SCK was low, hitting SCK up to nine times until SDA is observed high twice consecutively, or if that doesn't work up to nine times until SDA is observed high, and then issuing an I2C stop (the first case would ensure the stop would not occur at the right time to trigger a write; the latter case would allow a reset in case the I2C device was reading out lots of 0's). Is there any way to abort a write on an SPI part if one doesn't know how many bits have been clocked?

 

[simce]

There are no guarantees that the writes will be atomic. If power is cut in the middle of write, it can not continue unless you use large capacitors which is not recommended.
The solution is to have safeguard that will notify that the write process has ended successfully (write magic word at the end of write process)...
BR

 

[supercat]

The solution is to have safeguard that will notify that the write process has ended successfully (write magic word at the end of write process)...
BR

How much time and effort should one spend writing "magic words"?

I've changed the design since posting the original question, so I'm now using serial flash rather than EEPROM. The same general issue still applies, though the serial flash only needs a few microseconds to write a byte. It would be useful to know what to do with EEPROMs, however.

On many EEPROM devices, the datasheet time required to write one byte is the same as the time required to write a page (typically 5ms). Using magic words to signal data complete would necessitate replacing one 5ms page-write with two to four of them. To do it with only two writes, I think one would need two copies of the data and a flag indicating which one is valid; write the data, then the flag. If one can't afford to double-up the data, one would need to write into a special area the address of the data to be updated, along with the new data. Next, one would write a flag indicating that information was valid. Then one would update the data itself, and finally one would erase the "valid" indicator.

That seems like a lot of extra writing. With flash, where erasures are expensive, that sort of approach would be even more problematical, though my thought is that it should be possible to protect the supply enough to ensure a 7us write can complete. Does that seem safe?