EDK 11.5 Digilent Spartan 3e Starter DDR memory test fails

[akgs]

hi guys,

i am an undergrad student working on my thesis. i am new to edk and fpga based design. i have just created a project using edk bsb tool. i have a uart, block ram, and off chip ddr sdram in my system. after building the system and generating the bitstream, i am not able to get the memory test working. it says ddr sdram test fails over the hyperterminal. could you please help me with this problem? i have been struggling for many days trying to find a proper solution as i have not done anything apart from using the given components in the system.

thanks!

 

[Rob B]

This sounds similar to the rather odd problems I was getting with my project. I had lots of strange behaviour due to the DDR SDRAM controller that XPS Base System Builder Wizard was defaulting to.

The controllers, mch_opb_ddr v1.00.c and v1.00.b did not work with the Micron MT46V32M16-6T on the 3E Revision D starter kit.

My solution was to use mch_opb_ddr v1.00.a (Note the "a").

I have posts on the Xilinx forum about it and sent Goran Bilski some files to loot at. I think it might have been a timing issue but I didn't have time to look into it.

Other issues were the Microblaze seemingly hanging when I added more IP to the build. We suspected it was due to the way I was handling FSL communications and I spent weeks looking at the wrong things.

I don't have my build files here and I can't remember (a few years ago now!) where to edit the DDR controller revision but you should be able to search for it.

Oh! It wasn't version 11.5 I used so the revision of the controller might be different.

Hope that fixes your problem .

 

[akgs]

Re: EDK 11.5 Digilent Spartan 3e Starter DDR memory test fai

hey thanks rob,

does this problem have anything to do with digilent boards? coz i have seen in some forums where they have stated that digilent boards are prone to timing errors when compared to their xilinx counterparts.

 

[Rob B]

I just edited my post when you were replying there, I wasn't using 11.5 but 9.1, I think. The controller revision might be incremented now.

I was indeed using a Digilent board!

I forgot about this bit until I started reading over notes...

You may also want to add the following lines to the UCF.

PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED
PARAMETER C_PHASE_SHIFT = 45"

 

[akgs]

Re: EDK 11.5 Digilent Spartan 3e Starter DDR memory test fai

I have tried everything with this digilent kit, it doesnt work. Surprisingly my friend had Spartan-3E Xilinx manufactured board, and the memory test passed in that. I have no idea why it doesnt work in this digilent board. And I am using MPMC memory controller, most of the help that is available online is for the older memory controller.
Is it related to pinout or timing constraints generated by the EDK software that is not matching the constraints of this board?

Thanks

 

[Rob B]

I think it is down to the memory part timing specifications.

Just so it is documented, what are the exact part numbers of the memory devices?

Did you try the modification to the UCF?

Are there no other controllers available?

You could replace the memory part as a last resort. You'll probably get better marks for solving a problem without resorting to SMT rework though .

 

[akgs]

Re: EDK 11.5 Digilent Spartan 3e Starter DDR memory test fai

What constraints in the UCF should I modify? I am sorry, but I not sure which parameters to change like timing or pinouts.

I tried changing the phase shifts of the DCM output to 45, 60, etc. It didnt work. I even tried changing the jumper settings for M0 and M2. Nothing seems to work for this board.

I dont think there are any other controllers available for DDR. What can possibly go wrong with a different board which has FPGA identical parts and speed grades? I even checked out the board schematics, and the pinouts for the DDR are absolutely identical.

Thanks

 

[Rob B]

If it is exactly the same memory part it could be something critical in the PCB layout although I suspect not. The boards are probably designed from a Xilinx reference design.

I don't have the software to try this myself at the moment . I'd be suprised if they had removed the older DDR controllers from it though. If I remember right, I didn't find the controller in the wizard, I changed it manually.

 

[akgs]

Re: EDK 11.5 Digilent Spartan 3e Starter DDR memory test fai

I tried with another digilent board with a speed grade of 4C, (i think C stands for commercial) and the memory test passed in that as well. My digilent board has a speed grade of 5C/4I (guess I stands for industrial). Will that make a difference?

The memory test has so far passed with the same memory controller with 2 other boards. One which is manufactured by Xilinx with speed grade of 5C/4I, and the other which is manufactured by digilent with the speed grade of 4C.

My digilent has a speed grade of 5C/4I with exactly the same FPGA part (500E), and schematics. But memory test doesnt work. I suspect as you said it might be a PCB layout fault as even the memory part is the same. But I am not a 100% sure.

Thanks