"Edge not allowed in level-sensitive path" in comp

[jay_ec_engg]

While compiling my verilog testbench i am gettting error

"Edge not allowed in level-sensitive path"
What can be the reason ?

 

[Big Boy]

Re: "Edge not allowed in level-sensitive path" in

Can you give a snippet of your source code? It's hard to tell without seeing what's wrong.

I guess that you have, for example, a level-sensitive register (i.e. level-sensitive latch) and you are trying to assign a value to it using an edge-sensitive declaration.

 

[semiconductorman]

Re: "Edge not allowed in level-sensitive path" in

Do u get this when compiling/simulating the code ???? which simulator , if you can share the tb code ?

 

[jay_ec_engg]

Re: "Edge not allowed in level-sensitive path"

When I am trying to simulate this test bench at that time its showing the following error.... "Edge not allowed in level-sensitive path".. can anyone help me?

-----------------------------------------------
module Temp (clk,
enableN,
data );

input clk;
input enableN;
output data;

reg [15:0] temp; //specify from within the test bench

assign data = !enableN ? temp[15] : 1'bz;

always @(negedge clk) if(!enableN) temp = #35 {temp[14:0],temp[15]};

specify
specparam busOff = 40;
specparam zero = 0;

(posedge enableN *> data) = (zero,zero,busOff);

endspecify

endmodule // Temp

 

[Big Boy]

Re: "Edge not allowed in level-sensitive path" in

Not too sure, but could this be because you specify propagation delay between enableN raising edge and data outout, when data is assigned via a continuous assignment?

The delay you specify apply to a transition of enableN, when 'data' output depend on enableN level (instead of edge).

What if you specify the delay directly in the continuous assignment declaration?