Edge detection of a lo freq Clock using another high freq Clock

[imbichie]

Hi All,

Is it good to sample a Low Freq Clock (10 Mhz) with a High Freq Clock (87 Mhz).
The aim is to find the edge of the 10 Mhz clock and reset a counter which is running in 87Mhz.
Here the clocks are out of phase, and not a proper multiple.
So what i did was sample the 10 Mhz with the 87 Mhz,
is it synthesis or is it a good practice?

 

[barry]

You will need to use a synchronizer on your 10MHz clock. Then apply an edge-detect circuit to your synchronized signal.

 

[rca]

yes, there is no issue, you sample two times the 10MHz signal with the 87MHz signal, to avoid meta-stability and then you used this sample signal to detect an edge.

 

[imbichie]

I think, If i am assigning the 10MHz clock as D_in for sampling with 87MHz, it is a violation.
Means we cannot drive the clock path as the data path. Am i correct?
If that is the case what i will do?

 

[rca]

You could connect the 10MHz clock to the data input of the flop clocked with the 87MHz, there is no issue.
The clock tree tool will stop the 10MHz properly.

 

[imbichie]

Hi rca,
I didn't get what this means?

The clock tree tool will stop the 10MHz properly

 

[rca]

The clock tree tool will correctly equilibrate the tree.