leelahan
Newbie level 2
Position Title: EDA R&D Engineer (Library Characterization)
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Job Description:
The position requries timing (Dotlib CCS, ECSM) characterization of standard cell libraries for high-end micro processor designs at start of the art technology nodes. . This involves in running the in-house tools to generate timing views, comparing with transistor level timing and debugging the coded tests, arcs and other issues.
Desired Candidate Experience
This position requires prior experience in timing characterization of standard cell libraries and running related EDA tools. Candidate also needs to have strong understanding of Timing Analysis tools and delay models. Candidate should have B.Tech + 5 years experience and M.Tech + 3 years of experience.
Position Title: EDA R&D Engineer (Timing AE)
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Job Description:
The position requries qualification and support of STA and SSTA Timing Tools and methdologies. It will include one or more of the following responsibilities: supporting customers to resolve their issues, methodology qualification and development.
Desired Candidate Experience
An AE role can be very challenging and can be key to the EDA SW development team. We are looking for an individual who enjoys working in an AE role and uses the position to drive development. This role will require you to be accountable for individual or team results. As an individual contributor working as part of a team, this role will require you to absorb professional knowledge quickly, develop skills, and draw upon professional concepts to collaborate with others; guide other team members; identify problems, analyse causes and recommend solutions to job related problems; challenge the validity of given procedures and processes with the intent to enhance and improve; have a positive impact on customer satisfaction, business and business measurements; coordinate activities of less experienced or less knowledgeable team members, as required. The candidate should understand chip design fundamentals, and have had experience with design tool support. Experience with timing tools and concepts required. Excellent communication skills and flexibility is required.
Position Title: EDA Verification SW/UI development
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Job Description:
A strong C++ developer to work on developing and maintaining an electronic design automation visualization tool. A self motivated candidate must have a strong academic background in computer science or a related field. The job’s main focus is performance and thus requires knowledge of algorithm complexity, data structures, graph theory and discrete logic. Programming skills needed are: C, C++, STL, X11 based GUI toolkits (preferably Qt), IPC, Multi-threading, Unix development environments and tools such as shell scripting, make, Emacs/VIM (or other Unix IDE), lex/yacc.
Desired Candidate Experience
“Necessary Skiils: Experience and full command of the C and C++ language (near expert) Experience debugging C and C++ programs with visual and/or command-line debuggers C and C++ basics, static/dynamic memory management, pointers, arrays, strings, preprocessor OO: C++ classes, methods, templates, virtualness, references, constructor/destructors, in-line, overloading, static, protections, inheritance, exceptions Code performance issues Code debug, analysis, core-dumps,
Experience and full command of data structures and the STL,performance trade-offs, design, etc.
Software development “”best practices”", design issues, architecture Excellent communication/support skills Open to working on documentation, examples, presentations, etc. Desirable Skills: Logic Design, VHDL experience Logic Verification Experience Cycle or Event Simulation Writing/using testbench code
Experience with the open-source cook compile tool Experience debugging threaded programs Experience with Perl Experience with the PSL language
Position Title: EDA Methodology Engineer (PSDP)
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Job Description:
The position requires working with Vendor tools (Cadence/Synopsys) and methodologies for our OEM ASICs customers in Logical/Physical Synthesis domain.
Desired Candidate Experience
The candidate should have hands on experience in logic synthesis, placement and static timing analysis. The person should have motivation to lead a team and take it to the next level of owning worldwide responsibilities. This role requires excellent communication skills and person should be willing to work across different geographies. It also demans local and global collaboration with our internal as well as external (customers) designers. The person should be comfortable in adapting to new priorities in current fast changing business environment.
Position Title: EDA Methodology Engineer (Routing)
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Job Description:
The position requires working with cutting edge (32/22nm) routing tools and developing methodologies for ASICs/Processors. Support to our internal physical designers would be integral part of this role.
Desired Candidate Experience
The candidate should have hands on experience in routing (65nm and below). Knowledge in placement and static timing analysis domain is desirable. The person should have motivation to own worldwide responsibilities. This role requires excellent communication skills and person should be willing to work across different geographies. It also demans local and global collaboration with our internal as well as external (customers) designers. The person should be comfortable in adapting to new priorities in current fast changing business environment. As routing is getting complex with each technology node, the candidate should be self-motivated to keep up with the new trends in this domain.
If you find this position to be interesting and willing to explore your career with our client, kindly send us your updated profile mentioning. Also, it would be greatly appreciated if you refer any of your friend or colleague who is looking for a change, having the same experience.
For Any clarification or response, Pls write to han.leela@gmail.com
Thanks & Regards
Leela
Client Manager – Executive Search
han.leela@gmail.com
*************************************************
Job Description:
The position requries timing (Dotlib CCS, ECSM) characterization of standard cell libraries for high-end micro processor designs at start of the art technology nodes. . This involves in running the in-house tools to generate timing views, comparing with transistor level timing and debugging the coded tests, arcs and other issues.
Desired Candidate Experience
This position requires prior experience in timing characterization of standard cell libraries and running related EDA tools. Candidate also needs to have strong understanding of Timing Analysis tools and delay models. Candidate should have B.Tech + 5 years experience and M.Tech + 3 years of experience.
Position Title: EDA R&D Engineer (Timing AE)
**************************************
Job Description:
The position requries qualification and support of STA and SSTA Timing Tools and methdologies. It will include one or more of the following responsibilities: supporting customers to resolve their issues, methodology qualification and development.
Desired Candidate Experience
An AE role can be very challenging and can be key to the EDA SW development team. We are looking for an individual who enjoys working in an AE role and uses the position to drive development. This role will require you to be accountable for individual or team results. As an individual contributor working as part of a team, this role will require you to absorb professional knowledge quickly, develop skills, and draw upon professional concepts to collaborate with others; guide other team members; identify problems, analyse causes and recommend solutions to job related problems; challenge the validity of given procedures and processes with the intent to enhance and improve; have a positive impact on customer satisfaction, business and business measurements; coordinate activities of less experienced or less knowledgeable team members, as required. The candidate should understand chip design fundamentals, and have had experience with design tool support. Experience with timing tools and concepts required. Excellent communication skills and flexibility is required.
Position Title: EDA Verification SW/UI development
*******************************************************
Job Description:
A strong C++ developer to work on developing and maintaining an electronic design automation visualization tool. A self motivated candidate must have a strong academic background in computer science or a related field. The job’s main focus is performance and thus requires knowledge of algorithm complexity, data structures, graph theory and discrete logic. Programming skills needed are: C, C++, STL, X11 based GUI toolkits (preferably Qt), IPC, Multi-threading, Unix development environments and tools such as shell scripting, make, Emacs/VIM (or other Unix IDE), lex/yacc.
Desired Candidate Experience
“Necessary Skiils: Experience and full command of the C and C++ language (near expert) Experience debugging C and C++ programs with visual and/or command-line debuggers C and C++ basics, static/dynamic memory management, pointers, arrays, strings, preprocessor OO: C++ classes, methods, templates, virtualness, references, constructor/destructors, in-line, overloading, static, protections, inheritance, exceptions Code performance issues Code debug, analysis, core-dumps,
Experience and full command of data structures and the STL,performance trade-offs, design, etc.
Software development “”best practices”", design issues, architecture Excellent communication/support skills Open to working on documentation, examples, presentations, etc. Desirable Skills: Logic Design, VHDL experience Logic Verification Experience Cycle or Event Simulation Writing/using testbench code
Experience with the open-source cook compile tool Experience debugging threaded programs Experience with Perl Experience with the PSL language
Position Title: EDA Methodology Engineer (PSDP)
*****************************************
Job Description:
The position requires working with Vendor tools (Cadence/Synopsys) and methodologies for our OEM ASICs customers in Logical/Physical Synthesis domain.
Desired Candidate Experience
The candidate should have hands on experience in logic synthesis, placement and static timing analysis. The person should have motivation to lead a team and take it to the next level of owning worldwide responsibilities. This role requires excellent communication skills and person should be willing to work across different geographies. It also demans local and global collaboration with our internal as well as external (customers) designers. The person should be comfortable in adapting to new priorities in current fast changing business environment.
Position Title: EDA Methodology Engineer (Routing)
*********************************************************
Job Description:
The position requires working with cutting edge (32/22nm) routing tools and developing methodologies for ASICs/Processors. Support to our internal physical designers would be integral part of this role.
Desired Candidate Experience
The candidate should have hands on experience in routing (65nm and below). Knowledge in placement and static timing analysis domain is desirable. The person should have motivation to own worldwide responsibilities. This role requires excellent communication skills and person should be willing to work across different geographies. It also demans local and global collaboration with our internal as well as external (customers) designers. The person should be comfortable in adapting to new priorities in current fast changing business environment. As routing is getting complex with each technology node, the candidate should be self-motivated to keep up with the new trends in this domain.
If you find this position to be interesting and willing to explore your career with our client, kindly send us your updated profile mentioning. Also, it would be greatly appreciated if you refer any of your friend or colleague who is looking for a change, having the same experience.
For Any clarification or response, Pls write to han.leela@gmail.com
Thanks & Regards
Leela
Client Manager – Executive Search
han.leela@gmail.com
