Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

ECRL Design, Finding POWER DISSAIPATION ??? HOW TO??

Status
Not open for further replies.

gezzas525

Full Member level 3
Joined
Mar 14, 2002
Messages
150
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,296
Activity points
1,740
--------------------------------------------------------------------------------

Hi Iam doing ECRL low power design, and was trying to find a good way of calculating power dissipation in CMOS and ECRL circuits so that a comparison in power can be made between them. I used this method for calculating the power dissipation in the CMOS circuit http://www.stanford.edu/class/ee315/handouts/HO35_Power_Measure.pdf
however this method assumes the supply is fixed but in ECRL Iam using a ramp clock rise, hold, fall and wait. Where during rise it consumes energy and during fall it recovers it back into the circuit, obviously there is goin to be some loss being the difference between what went into the circuit and what was recovered. Can anyone find a way to apply this method, Ive tried integrating the supply in sections and multiplying the result with the rest of the equation.

THANKS
KLEOS
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top