dynamic VHDL PCI-core testbench....or anything...

[vahidkh6222]

pci testbench

hi all.
in my BSc project i must implement a 33Mhz PCI target interface using a spartanII FPGA.
i have done the PCI-core VHDL design.... i did this step by step just like specification in a hierarchical manner...
but know i need a dynamic testbench to test wut i developed. i dont exactly know the real transactions occur on a bus by master, interrupt controller AND etc...

does anyone know a ready to use testbench or at least have a refrence to implement such a functionality?.

any better ideas?!!

thanks in advance.

 

[saho]

vhdl pci

Do take a look at the following documents.

**broken link removed**

https://ntserv1.ida.ing.tu-bs.de/EGSE/pci_64_docu/altera/ug_pcitestbench.pdf

 

[kevinbrace]

pci core testbench

Hi vahidkh6222,

Although currently only for Verilog, and VHDL porting isn't quite ready yet, but you may want to consider BDS XPCI PCI IP core we have developed.
BDS XPCI PCI IP core is a Xilinx (TM) LogiCORE (TM) PCI compatible PCI IP core.
We offer this PCI IP core for as little as $100 for non-commercial, non-profit, personal use.
For more information, visit https://www.bracedesignsolutions.com.


Kevin Brace

hi all.
in my BSc project i must implement a 33Mhz PCI target interface using a spartanII FPGA.
i have done the PCI-core VHDL design.... i did this step by step just like specification in a hierarchical manner...
but know i need a dynamic testbench to test wut i developed. i dont exactly know the real transactions occur on a bus by master, interrupt controller AND etc...

does anyone know a ready to use testbench or at least have a refrence to implement such a functionality?.

any better ideas?!!

thanks in advance.

 

[vahidkh6222]

ip core test bench

tnx kevin but.... i did this myself, i just need a testbench... for free, or at least much less expensive than this...

 

[lzh08]

pci controller vhdl download

you could look for it at www.opencores.org

 

[kevinbrace]

xilinx pci target non burst

Hi vahidkh6222,

I guess $100 for the PCI IP core + testbench is too much for you.
If you consider the time it takes to develop the verification models, I personally think $100 is worth the cost even if you don't use the PCI IP core itself.
Anyhow, I will explain the PCI testbench you will be getting for $100.
The PCI testbench that comes with BDS XPCI PCI IP core consists of a Host to PCI bridge, PCI arbiter, and target only PCI device model.
From the Host to PCI bridge, you can initiate various PCI transactions like a configuration read cycle.
You can even initiate a long PCI burst transfer from the Host to PCI bridge with programmable byte enable, wait states, 1 bit parity error.
The target only PCI device model is mainly for the debugging of a bus master (initiator) PCI device, and it can be programmed to insert retry, wait states, disconnect style (Disconnect with Data or without Data), or read parity error.
These models were written in Verilog, and most of the VHDL porting has been finished, so as soon as you pay for the PCI IP core, you will get the VHDL version of the PCI testbench.
ModelSim is the only officially supported HDL simulator, but the PCI testbench itself should work with other HDL simulators (Verilog and VHDL).


Kevin Brace


--
Brace Design Solutions
Xilinx (TM) LogiCORE (TM) PCI compatible BDS XPCI PCI IP core available for as little as $100 for non-commercial, non-profit, personal use.
https://www.bracedesignsolutions.com

Xilinx and LogiCORE are registered trademarks of Xilinx, Inc.

tnx kevin but.... i did this myself, i just need a testbench... for free, or at least much less expensive than this...