dynamic latch comparator problem

[oskar11]

i made simulations of dynamic latch comparator. i connected vin- and vref- to vdd/2. if vin+ is greater than vref+, output is high but when vref+ is greater than vin+, output does not stay on zero, it follows clock signal. How can a solve this problem???

 

[jiangxb]

can you give the schematic and simulation results and explain in more detail?

 

[mahgoub]

i don't think you have a problem first of latch comparators are implemented by two inverters connected in positive feedback connection they must be set every clock cycle to a certain value(vdd) so the comparator has two phases set to one
then the comparator output so in first case the is one
then it is set to one also in the second case the comparator is zero but in the set phase one so actually it is working fine second when you test a differential comparator the comparason is between the difference between each +,- so you should have
a common mode (dc input for the four inputs) and then the ac signal is compared .