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Dynamic comparator design for pipeline ADC

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analogman

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Now I design dynamic comparator for pipeline ADC.
But there are some problems.

comp1.gif


This is my design parameter.
Vdd = 3.3V (CM = 1.65V)
Vref+ = 1.9 V
Vref- = 1.4 V
Vin+ - Vin- ; ramp signal from -3.3V to 3.3V

1. This comparater generates 1/4Vref threshold voltage if I design W2/W1=0.25.
Simulation with only compater was well done.
But I put NAND gate at the output node of comparater, the threshold
voltage has shifted!! I can't find the reason at all so it troubles me...
Anyone tells me about the reason please.

【Only comparator simulation】
hakei_correct1.gif

【with NAND gate simulation】
hakei_error1.gif


2. I use this comparater directly linking to MDAC. But some papers use S/H
configuration. I don't know which is correct...
I think to use S/H configuration will become large input capacitance.

Sorry, for my poor english and explanation.
I want your help!
 

mkhafaji

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Dynamic comparator

I think you have some problems in biasing your nand gate. because your nand input voltages don't match output nodes of your comparator.
using capacitor is for this reason and its role is dc level shifter.
try with changing your biases or adding swithes and capacitors between nand and comparator
 

philipwang

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Re: Dynamic comparator

1. Advise to select large W/L ratio in NAND transistor.
2. SC is added between comparator and NAND? Which paper mentions it? The configuration of comparator connects to NAND directly seems no problem.

analogman said:
Now I design dynamic comparator for pipeline ADC.
But there are some problems.

comp1.gif


This is my design parameter.
Vdd = 3.3V (CM = 1.65V)
Vref+ = 1.9 V
Vref- = 1.4 V
Vin+ - Vin- ; ramp signal from -3.3V to 3.3V

1. This comparater generates 1/4Vref threshold voltage if I design W2/W1=0.25.
Simulation with only compater was well done.
But I put NAND gate at the output node of comparater, the threshold
voltage has shifted!! I can't find the reason at all so it troubles me...
Anyone tells me about the reason please.

【Only comparator simulation】
hakei_correct1.gif

【with NAND gate simulation】
hakei_error1.gif


2. I use this comparater directly linking to MDAC. But some papers use S/H
configuration. I don't know which is correct...
I think to use S/H configuration will become large input capacitance.

Sorry, for my poor english and explanation.
I want your help!
 
Last edited by a moderator:

sunking

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Dynamic comparator

yes, the nand input voltages don't match output nodes of your comparator.
you should add a stage, such as a single stage diff amp to meet.
 

analogman

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Re: Dynamic comparator

mkhafaji, philipwang, sunking

Thank you for replying!
and Sorry to be late for my replying.

> philipwang

1. I tried large W/L ratio in NAND transistor.
But the problem remained.

2. SC isn't added between comparator and NAND.
Comparator is used for amp in sampl hold circuit.
For example, in cline's paper (figure in page 38 ).

https://kabuki.eecs.berkeley.edu/~cline/slides/cicc/interview.38.html

I have seen that with S/H configuration, input offset is reduced.

> mkhafaji, sunking

Thank you for advice.
I added diff amp(but verilog-A model) between comparator and NAND.
And threshold voltage didn't shifted !

So I found my Nand input voltages don't match output nodes of my comparator.

Thank you for everyone!:D
 

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