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Duty Cycle decision in Design

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legalist

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I want to know how duty cycle of clock is decided for a particular IC design ?
 

goldsmith

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Dear legalist
Hi
What do you want to do accurately ?
Please , give me a bit more explanation .
Regards
Goldsmith
 

legalist

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Dear legalist
Hi
What do you want to do accurately ?
Please , give me a bit more explanation .
Regards
Goldsmith

Hi,

I just want to know that FF works at posedge of clock and posedge occurs after every Clock period irrespective of duty cycle.So what does this duty cycle effect for a particular design?

and what are the factors on which it depends that how much duty cycle to use for a particular design?

Thanks and Regards
Legalist(Deepansh)
 

goldsmith

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Is your mean flip flop with FF ?
An important think :
if you change the duty cycle , naturally , the falling edge will accept affects ! and if your IC can work with rising edge it is not important . but if your IC will work with rising edge it will has many effects on it's procedure .
Best Wishes
Goldsmith
 

legalist

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Is your mean flip flop with FF ?
An important think :
if you change the duty cycle , naturally , the falling edge will accept affects ! and if your IC can work with rising edge it is not important . but if your IC will work with rising edge it will has many effects on it's procedure .
Best Wishes
Goldsmith


ya I have used FF for flip flop.Didn't got u with "falling edge will accepts affects!".Can you be somewhat more elloborative

Thanks :)
 

goldsmith

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Again Hi
If you change the D.C , thus , the on time will change simply . but the start time didn't change . so the falling edge will change ( it's time ) .
Respect
Goldsmith
 

dick_freebird

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Duty cycle per se may not be significant, but every FF has
a setup time, hold time and minimum clock pulse width that
have to be respected. So there will be some minimum duty
which is the worst case time divided by period.

Sometimes you see logic that clocks using both edges (like
anti-metastability chains) meaning that the duty range has
two constraints.

A 50% clock has maximum margin against pulse extinction
in long taper chains where asymmetries may accumulate.
I have seen this in a challenging high speed (for the node)
digital design where a cascade of noninverting buffers was
the initial choice for the clock tree; TPLH-TPHL skew did
accumulate to the point that one phase became malformed.

Plus you get no arguments from anybody about a square
clock. Sometimes that's reason enough.
 

goldsmith

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Sometimes you see logic that clocks using both edges

Dear dick_freebird
Hi
What do you mean by that clearly ? is you mean that , some of logic Ic's have two clock pines ? one of them for rising edge , and the other , for falling edge ? if yes , can you introduce some of them to me , please ?
Best Regards
Goldsmith
 

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