I want to design 30% duty cycle using VHDL. My clock frequency is 50MHz and frequency divider is 500Hz. Here I attach code for 10% duty cycle. I want change this code from 10% duty cycle to 30% duty cycle. Please someone help me.
Why don't you add another STD_LOGIC input on the entity declaration, acting as a selector ?
On the process implementation, use a if...end if to switch among them accordingly.
Actually, I need to design variable duty cycle, which is 10%, 30%, 50%, 70% and 90% from variable frequency. First of all, I need to design for fixed duty cycle. For variable frequency, I already got the answer. Now, I stuck in a variable duty cycle. By the way, thanks for your reply.
The general PWM would be an accumulator and a comparator.
To get variable frequency, you adjust the amount added to the accumulator each cycle.
To get variable duty cycle, you adjust the comparator.
This method introduces some small amount of error, but it is usually very small.
You can also do this by adjusting the terminal count of the accumulator, as you have done. But then you end up with a multiplier to get the value to use for the comparator.
There is also a method that works for a specific set of frequency/ratio combinations, if the required intervals can be generated by the clock.
Actually I don't know how to start it. I don't know how to related my variable frequency with variable duty cycle. It's been like this, for example, if 1 kHz freq, it will be 10%, 30%, 50% and so on for duty cycle.
By saying "10%, 30%, 50% and so on" you're lacking the clarity required for a VHDL code specification. Does it mean 10, 30, 50, 70, 90 and no other values?
Presently your design has neither a frequency nor a duty cycle input. For both quantities, you need to specify range and resolution respectively a word width.
vGoodtimes suggested to set the frequency by using a NCO scheme (accumulator with variable increment) opposite to the usual setting of an integer period. Need to find out if this scheme is useable for your application.