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Duration of SYNC pulse in L5991 PWM controller?

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cupoftea

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Hi,
We have a SMPS in which an L5991 PWM controller is being SYNC’d by the PWM O/P of a ML4800 PFC/PPWM combo controller.
The PWM O/P of the ML4800 is divided down and then sent to the SYNC pin of the L5991.

So the L5991 is a “slave”. The L5991 datasheet does not make it clear whether the PWM output gate drive pulse (of the L5991) is held low during the “high” time of the SYMC pulse received?
Page 8 and 9 speak about it but are ambiguous.

L5991 datasheet

ML4800 datasheet


The ML4800 is a combo PFC and PWM controller, but we are instead using the L5991 as the PWM controller, and using the ML4800 to SYNC the L5991. (though we are using the ML4800 as the PFC controller)
 

Why ambiguous? The datasheet has a detailed functional schematic. The output is not held low during sync pulse, its leading edge ends pwm cycle, output is switched on after td, no matter how long the sync pulse lasts.
 
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