dumping RTL in unique coding style

[jitendra]

I am writting TCL based utility which will parse the RTL files for searching instance names etc. Problem I am facing with this utility is to take care of various coding styles:

For example, Component instance can be written in different ways as:

Comp_name inst_name (

Or

Comp_name inst_name
(

Or

Comp_name
inst_name
(



Etc.



Is there any command / tool which will read this verilog file and give output file which will have consistency in coding style?

Thanks for your help.

Regards,
Jitendra

 

[nand_gates]

Simple is you write a perl script to do this!

 

[jitendra]

Hi,
I can write TCL or Perl script but this is just one of the many issues due to inconsistancy in coding style. Some standard tool is required to take care of all such issues.
Thanks for your suggestion.

Jitendra

 

[leeenghan]

Hi,

You can write a pre-processor, or you can continue reading (ignore \n ) until you see a ";".

I prefer a pre-processor method. The goal is to translate a verilog code to one line per statement. Using perl or awk you can do this in not more than 100 lines of code.

Regards,
www.eda-utilities.com

 

[r63511]

I used to write script in multi-line mode to parse the whole design file and make mapping with the gatelevel file for ECO fix, and compared with other script language, perl is the quickest and easiest to write and debug for this task. I highly recommend the method.

 

[nand_gates]

Try lex & yaac! With little practice you can do whatever you wish. But this one is
a hard way. OR using tcl remove '\n' and get the whole code on single line before
parsing this will make the code style independent!

 

[umairsiddiqui]

see
https://www.veripool.com/verilog-perl.html
there is module

Verilog::Netlist

builds netlists out of Verilog files. This allows easy scripts to determine things such as the hiearchy of modules.