Dummy transistors connection

[elbadry]

Dear All,

In TSMC 0.18u process, how do I connect the dummy transistors' gates to vdd or gnd?

Is direct connection feasible? ( i think there would be an ESD issue here )

Concerning soft-pulls, how can they be implemented? what are the constraints/design considerations for them?


Thanks...

 

[neoflash]

Their digital library will have soft_vss, soft_vcc.

 

[vijay.kumarreddy]

For PMOS ,Short all terminals and connect to the VDD

Fpr NMOS ,Short all terminals and connect to the GND

vijay

 

[YESH_23]

as of normal ckts vijay.kumarreddy is correct but some special ckts put a word to the schematic designer also might help u

 

[vbhupendra]

PMOS to vdd
and NMOS grounded

 

[papertiger]

Are you talking core cell or IO cell?
connect directly to VDD/GND in core cells.
float the dummy transitor in IO cell.

 

[Son]

PMOS to Vdd, NMOS to Vss.

 

[shiva4u]

Hi tiger,
I didnt get your point, why you asked to float dummy in Io cells. If you think of esd then all it wont give problem right. because the source and drain of dummy will be the path for the ESD current and the poly won't be affected. If there is any other issue please let me know.
Thanks & Regards,
Shiva.

 

[layout_designer]

connect source drain and gate of dummy Nmos trasistor to Vss and pmos to vdd respectively.

all three terminals of a transistor must be shorted to one node.

hope this clarifies a little

 

[birdiee470]

for PMOS transistor connect the gate to VDD and for NMOS transistor, connect the gate to GND

 

[vijay.kumarreddy]

Hi papertiger,

Ur not suppose to leave any device floating,even its dummy,if its floatinf it will acts as an antenna and collects the charge near by surrondigs , and u cannot predect the state of the operating conditoin of that particular MOS on Silicon,We have faced this practically

vijay

 

[lavitaebelle]

AS far as my experience goes in ICs should not connect the PMOS and NMOS gates to the supplies directly. There must be a soft pull up through a resistor. This is because of ESD issues. I dont exactly know the reason behind this. I presume a low pass filter effect.

As Vijay rightly pointed out, no transistor gate must be left floating. The drain/source can be floating or connected directly to supply/ground but gate voltage must be defined.

 

[wan]

We can see the layout of pcell----rfnmos and rfpmos from TSMC, it only extended DIFF IMP area and added two more poly rails around mos device, without connecting dummy poly with other wires.

 

[omsi]

Dear All,

In TSMC 0.18u process, how do I connect the dummy transistors' gates to vdd or gnd?

Is direct connection feasible? ( i think there would be an ESD issue here )

Concerning soft-pulls, how can they be implemented? what are the constraints/design considerations for them?


Thanks...

dummies are only used in Matched pair & it is most oftenly used in analog circuts. In analog circuts each matched pair id surronded by double gaurd rings & the dummies are connected to gaurd rings & inturun the rings are connected to vdd & vss respectively.