dummy NFET with grounded gate = ESD risk?

[quantized]

Question: is it an ESD risk to have an NFET with its gate grounded even when its drain is grounded too?


Argh!

I've just finished up a layout for a tech where the minimum diffusion separation (i.e. minimum STI width) is much larger than the minimum contacted gate pitch. This means you can improve density by putting a "dummy gate" between nearby unconnected diffusion regions. I did this with the NFETs in the latches/registers; there are tons of them so the improvement was substantial (10-15%). In all instances where I did this at least one of the diffusion regions was already grounded to begin with; the other one is an unrelated signal node.

Unfortunately, days from tapeout, I discovered that the foundry advises against this due to ESD risk -- the gate is connected directly to the GND pin. The GND pads have ESD protection (diodes and some other foundry magic) but the foundry advises that supply-connected gates should have a 2kohm resistor inline as well. They don't say if this still applies when the NFET with a grounded gate also has a grounded source. I'm having trouble seeing how ESD damage would occur in this situation, but I'm not an ESD expert.

Is this something I need to worry about? Unfortunately there is definitely no room in the layout to bring in an additional "resistive GND" supply to every single latch.

If this is bad practice, why doesn't it apply to MOSCAPs used for decoupling? Those have their gates tied to VDD, which seems like it would be even worse.

Thanks,

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Here's an example of the layout, Mead-Conway color scheme (pink poly, green diffusion, blue Metal-1). The ground node is labeled, as is the node "x" which is some unrelated node. Simply deleting the ggNMOS is a DRC violation since the grounded diffusion contact would be too close to the contact for node "x". Node "z" is the gate of a nearby (unrelated) pulldown NFET for node "y".

 

[erikl]

If this is bad practice, why doesn't it apply to MOSCAPs used for decoupling? Those have their gates tied to VDD, which seems like it would be even worse.

MOSCAPs for decoupling usually have enough capacitance, so are not so prone to ESD or antenna problems.

Anyway, I don't think your space-saving method represents a big jeopardy. Still - if allowed by design rules - could you put salicide blocking layer over those gates? So you'd create at least some resistance between gate and gnd.

 

[quantized]

MOSCAPs for decoupling usually have enough capacitance, so are not so prone to ESD or antenna problems.

Ah, that's good to hear. These "spacer" gates always appear in large (32 or more) clusters placed close to each other and with the ggNMOS gates connected by low-impedance metal-1. If you merge them together the total gate capacitance is substantially more than a small MOSCAP.

Still - if allowed by design rules - could you put salicide blocking layer over those gates? So you'd create at least some resistance between gate and gnd.

That's a very interesting idea -- unfortunately stuff is packed much too closely for that. The salicide layer is a low-resolution mask so the design rules require that it totally encloses any diffusion region by a very large (~5 gate lengths) margin. If two transistors are butted you have to either salblock them both or neither. Good idea, though!

 

[dick_freebird]

ESD is about current but everybody talks about the voltage.
Where is your current path in an all-shorted-to-GND device?
Right.

Now, lonely gates with a huge chunk of metal can be an
antenna charging threat. But that is not ESD.

An implanted resistor region makes a swell antenna diode.
A floating (like poly) resistor is not going to prevent
antenna damage because the current is low and there's
no place but the gate for it to go, any limiting will be too
late. But putting it there may "fix" a violation flag if the
rules are dumb.