DUAL-PORT SRAM using 2Read/Write ports

[art_hardware]

Hi,
I want to work on dual-port SRAM using Cadence tool. Can you explain me how a dual-port with 2RW works? I want to know how the simultaneous read and write operation takes place in the 2RW dual-port SRAM.

 

[sky_siliconthink]

First, you have to understand the operation of single-port SRAM. A brief picture:

Second: You can treate Dual-port SRAM as a sram cell with two independent r/w access interface. A brief description:

For detailed explain, you can refer to this link (at about 00:22:00, it talks about operation of dual-port sram):

 

[im_pam]

To make the working of SRAM cell, you need to use the write driver for writing the data into the 6t sram bit cell and for reading the data you have to use the sense amplifier.

There are 2 signal: while writing the data, write enable is enabled and sense amplifier (SA) clock remains low . However in next clock cycle write enable signal which is connected to the write driver is disabled and after precharging the bitcell .... SA is turned on through SA enable signal and then data written inside the bitcell is sensed by it.

For doing all this,you have to first go through the basic 6t sram and implement single 6t cell in the cadence virtuoso tool. Then make simple precharge circuit, write driver. current latch SA and check its functionality.


regards