Sep 25, 2003 #1 R roadrunner Junior Member level 3 Joined Oct 31, 2001 Messages 25 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 147 I know this issue is kind of old? but anyone can provide some suggestion to design a dual port fifo with two different clocks input ?
I know this issue is kind of old? but anyone can provide some suggestion to design a dual port fifo with two different clocks input ?
Sep 25, 2003 #2 ttspice Member level 3 Joined Dec 24, 2001 Messages 64 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,288 Location Republic of Taiwan Activity points 555 yes, it 's pretty classical, see the attached SNUG paper.
Sep 25, 2003 #3 Al Farouk Full Member level 4 Joined Jan 13, 2003 Messages 191 Helped 16 Reputation 32 Reaction score 16 Trophy points 1,298 Location Egypt Activity points 1,854 Also Xilinx many App Notes about different usage of its dual port RAM as (FIFO, Bus Width converters, ..etc) you certainly will find good ideas help your topic.
Also Xilinx many App Notes about different usage of its dual port RAM as (FIFO, Bus Width converters, ..etc) you certainly will find good ideas help your topic.
Sep 25, 2003 #4 I it_boy Full Member level 3 Joined Jul 18, 2002 Messages 173 Helped 6 Reputation 12 Reaction score 2 Trophy points 1,298 Activity points 1,261 this webpage has some good resources about asynchronous fifos \hxxp://www.geocities.com/deepakgeorge2000/
this webpage has some good resources about asynchronous fifos \hxxp://www.geocities.com/deepakgeorge2000/