Aravind_Selvaraj
Newbie level 4
Hi everyone,
I am designing an analog system which requires a Verilog code that performs the following.
Inputs : clk1 (30Mhz) , clk2 (250Khz), reset ( So , the clk1 will complete 120cycles in the time clk2 completes one cycle)
Output : delay[7:0]
Problem : The output delay[7:0] should increment only if there is a posedge in both clk1 and clk2.
Clearer words : it should have a functionality like : always @ ( posedge clk1 && posedge clk2)
All suggestions welcome. (I'm also paralelly working on it
)
I am designing an analog system which requires a Verilog code that performs the following.
Inputs : clk1 (30Mhz) , clk2 (250Khz), reset ( So , the clk1 will complete 120cycles in the time clk2 completes one cycle)
Output : delay[7:0]
Problem : The output delay[7:0] should increment only if there is a posedge in both clk1 and clk2.
Clearer words : it should have a functionality like : always @ ( posedge clk1 && posedge clk2)
All suggestions welcome. (I'm also paralelly working on it
)