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| //source component
input Tx_fifo_write;
output Tx_fifo_full;
input Tx_fifo_wclk;
input [7:0] Tx_input_to_fifo;
reg [31:0] input_to_fifo;
reg [7:0] adc_value [0:3];
reg [1:0] idx = 0;
always @ (posedge Tx_fifo_wclk)
begin
if ((Tx_fifo_full == 0) && (Tx_fifo_write == 1))
idx <= idx + 1;
adc_value[idx] <= Tx_input_to_fifo;
end
always @ (posedge Tx_fifo_wclk)
begin
if (idx == 0)
begin
if(Tx_fifo_full == 1)
begin
Tx_fifo_write_in <= 0;
end
else
begin
Tx_fifo_write_in <= Tx_fifo_write;
input_to_fifo <= {adc_value[0], adc_value[1], adc_value[2], adc_value[3]};
end
end
end
dcfifo
#(
.intended_device_family ("Cyclone IV"),
.lpm_numwords(65536),
.lpm_showahead("OFF"),
.lpm_type("dcfifo"),
.lpm_width(32),
.lpm_widthu(16),
.overflow_checking("ON"),
.rdsync_delaypipe(4),
.read_aclr_synch("ON"),
.underflow_checking("ON"),
.use_eab("ON"),
.write_aclr_synch("ON"),
.wrsync_delaypipe(4)
)
Inst_RxFIFO (
.aclr(),
.wrclk(Tx_fifo_wclk),
.wrreq(Tx_fifo_write_in),
.wrfull(Tx_fifo_full),
.data(input_to_fifo),
.rdclk(Tx_fifo_rclk),
.rdreq((Tx_fifo_read) && (!Tx_fifo_empty)),
.rdempty(Tx_fifo_empty),
.q(Tx_output_from_fifo)
); |