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Dual active Bridge converter problems

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treez

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Hello,
We have just been sent a pspice/orcad simulation of a three phase, 200khz, 12kw, Dual Active Bridge (DAB) converter. (540Vin to 28vout)
All it is, is what it says it is, a full bridge on the primary, and another on the secondary, with the leakage inductances being relied upon to make it work as an SMPS.

Attached is an Ltspice simulation of a single phase DAB. (six of them)

From the simulations 1 to 6, are any of these incorrect? (ie bad phase shifting of the secondary fets etc?).

Also, we noticed on the pspice sim that we were sent, that they had only 1nH of secondary leakage inductance……a totally unrealistically small amount. Increasing the leakage to even 100nH drastically reduces the power throughput.

I have a suspicion that it isn’t realistic to achieve low enough secondary side leakage inductance to be able to make this converter viable.

Do you agree.?

They also told us that it didn’t matter how slow the fets’ antiparallel diodes were since they would never be reverse recovered…however, all resonant converters have modes of operation, (be it light load or transient operation) where they may suffer diode reverse recovery…do you agree?

Another point is that there is ZVS at primary fet turn on, but heavy switching loss at prmary fet switch off…do you think we need a capacitor across the primary side fets to relieve fet switch off switching loss?

(BTW, DAB smps is supposed to be a dab-hand at bidirectional power flow...boost up or buck down in either direction)
 

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treez

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Also, the DAB looks like a phase shift full bridge with the output inductor removed. I believe the above need to be phased as a PSFB.
 

asdf44

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This is an oldish thread but I recently inherited a DAB design and its FPGA control so I'm trying to catch up on the topology and clean up our design. I'm intimately familiar with our implentation at this point though lack the broader experience to completely contextualize what we did versus what some of the options were. I'd love to hear whether you used this at all or what you thought were the pros and cons of this topology.


On a quick look these simulations look "correct" and actually they're great simulations, running faster than what I put together in LTSPICE.

The dual active bridge, as I'm familiar with it is typically phase shifted with the neutral being the point where the primary and secondary switch simultaneously in a way that's constructive with respect to the voltage across the inductor. At this operating point flows equally in and out of the filter cap. But this is the downside - huge conducted losses as the inductor current is at its peak when no power is delivered (and grows if Vout increases). As the phase is shifted net current is delivered positively or negatively.

I don't understand why the design would be sensitive to secondary leakage when you have a primary inductor orders of magnitude larger...that makes no sense.

Yes caps on the primary should reduce primary losses as these simulations appear to be operating in a quadrant where stored current will charge/discharge those caps in a helpful way. With dead time of course.

This paper is a fantastic resource in general and also outlines various alternative modulation schemes to regulat phase shift:
https://www.pes.ee.ethz.ch/uploads/..._Active_Bridge_DC-DC_Converter_Topologies.pdf

This paper seems to cover basic phase shift quite well:
https://www-personal.engin.umd.umich.edu/~chrismi/publications/2008_1_4_IET_PE_DC_DC.pdf
 
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treez

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I don't understand why the design would be sensitive to secondary leakage when you have a primary inductor orders of magnitude larger...that makes no sense.
As you know, the primary and secondary have mutual flux which cancels each other out, so the large-ness of the primary inductance cannot stop sudden changes in the power current, because the power current doesn't "see" the primary inductance, it only sees the leakage inductance, you can see from numbers 1 and 2 of the top post sim that secondary leakage makes a big difference
 

mrinalmani

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Perhaps you forgot to refer the leakage inductances to one side of the transformer.
Although the leakage on the low-voltage side is only 100n, the turn ratio on this side is roughly 19 times smaller than the other side.
When referred to the HV side, this leakage gets multiplied N square times. i.e. 100x19x19 = 36uH. Total leakage as referred to the HV side = 3.5uH + 36uH = 41uH
The leakage of 3.5uH shown on the HV side (which appears large) is actually much smaller than the leakage on the LV side and therefore even a small variation in LV leakage results in large power throughput variation.

I totally agree that it is not possible to make such a low value of leakage inductance. The best that I would expect is nothing lower than 15nH.
On toroid cores with non interleaved winding, a good practical assumption of leakage inductance would be 1/50 to 1/100 of Xm.
For example if the magnetizing inductance Xm = 5uH, expect the leakage to lie between 50nH to 100nH
With interleaved winding, leakage would be around 1/200 to 1/400.
For Xm = 5uH, expect leakage to lie between 12nH to 25nH.
Of course there are sophisticated ways for reducing leakage, but in a normally wound transformer a 2% leakage (1/50) should be a good starting assumption. Most commercially available transformer datasheets also quote leakage between 1-3%.
1nH would mean 0.02% leakage! Far beyond even imagination...

- - - Updated - - -

Adding series ceramic capacitors will help cancel out the effect of leakage and will also make current waveform smoother
 
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