I am working on a High Frequency (3-4MHZ range) Half-Bridge SMPS where i have to drive high side and low side gates with PWM from dspic33f. Currently i am trying to minimize the power consumption by dspic33fj16gs502 controller by changing the PWM resolution as is stated by Microchip in TB062 document (page 5). But i am running into a problem that the output pwm is not stable, it deviates from its mean value which is highly undesirable in my case. Below is a snapshot attached of one of the PWM line output.
I tried to alter pwm resolution by two methods and both gave me the same result. following are the moethods used one at a time
1) by setting ACLKCONbits.APSTSCLR = 6 to divide auxiliary clock output by 2 while initializing auxiliary clock for PWM.
2) by using PTCON2bits.PCLKDIV = 1; to change pwm resolution to 2.08ns
Any help in this regard will be highly appreciated thanks,
It looks like the device implements fractional divider methods to achieve average time resolutions smaller than the system clock period. In this case, jitter will be an unavoidable side effect. But it's only a guess, I wasn't able to find the PWM generator details at a brief datasheet review. I think, Microchip didn't manage to present them clearly.
It looks like the device implements fractional divider methods to achieve average time resolutions smaller than the system clock period. In this case, jitter will be an unavoidable side effect. But it's only a guess, I wasn't able to find the PWM generator details at a brief datasheet review. I think, Microchip didn't manage to present them clearly.
I am not using any specific app from the datasheet, i am writing code myself for half brigde converter and for that i am using High-speed PWM in complementary mode. The switching frequency that is providing efficient results in around 3.5 MHZ. My main goal is to reduce the power consumption of dspic33fj16gs502 controller to the minimum possible value in No-load and Light-load condition.