DSPIC33CK128MP505

[PRATHAP96]

Hi,


Here, I have configure by input capture for using MCC melody to easy setup method. I have generated PWM to 50HZ. and capture the value but output is not occurred. I have attached the code for here. please check and let me help.

void SCCP1_InputCapture_Initialize(void)
{
// MOD Edge Detect; CCSEL enabled; TMR32 16 Bit; TMRPS 1:1; CLKSEL FOSC/2; TMRSYNC disabled; CCPSLP disabled; CCPSIDL disabled; CCPON disabled;
CCP1CON1L = 0x10; //The module is disabled, till other settings are configured.
//SYNC CLC2; ALTSYNC disabled; ONESHOT disabled; TRIGEN disabled; IOPS Each Time Base Period Match; RTRGEN disabled; OPSRC Timer Interrupt Event;
CCP1CON1H = 0x11;
//ASDG 0x0; SSDG disabled; ASDGM disabled; PWMRSEN disabled;
CCP1CON2L = 0x0;
//ICSEL None; AUXOUT Disabled; ICGSM Level-Sensitive mode; OCAEN disabled; OENSYNC disabled;
CCP1CON2H = 0x0;
//PSSACE Tri-state; POLACE disabled; OSCNT None; OETRIG disabled;
CCP1CON3H = 0x0;
//ICOV disabled; ICDIS disabled; SCEVT disabled; ASEVT disabled; TRCLR disabled; TRSET disabled; ICGARM disabled;
CCP1STATL = 0x0;
//TMRL 0x0000;
CCP1TMRL = 0x0;
//TMRH 0x0000;
CCP1TMRH = 0x0;
//PRL 0;
CCP1PRL = 0x0;
//PRH 0;
CCP1PRH = 0x0;
//CMPA 0;
CCP1RA = 0x0;
//CMPB 0;
CCP1RB = 0x0;
//BUFL 0x0000;
CCP1BUFL = 0x0;
//BUFH 0x0000;
CCP1BUFH = 0x0;

SCCP1_InputCapture_CallbackRegister(&SCCP1_InputCapture_Callback);

IFS0bits.CCP1IF = 0;
// Enabling SCCP1 interrupt
IEC0bits.CCP1IE = 1;

CCP1CON1Lbits.CCPON = 1; //Enable Module

}

void __attribute__ ( ( interrupt, no_auto_psv ) ) _CCP1Interrupt (void)
{
unsigned t1,t2;
if(NULL != SCCP1_InputCaptureHandler)
{
(*SCCP1_InputCaptureHandler)();
t1=SCCP1_InputCapture_DataRead();
t2=SCCP1_InputCapture_DataRead();
}
IFS0bits.CCP1IF = 0;
if (t2>t1)
{
result=t2-t1;
}
else
{
result=(0.00025-t1)+t2;
}
}

the result is the input capture.


The

 

[Aussie Susan]

Please show the CONFIG items and the rest of the code.
Is the ISR being called?
How is 'result' declared?
How are you determining that "...output is[sic] not occurred"?
Susan

 

[Aussie Susan]

Also posted to https://forum.microchip.com/s/topic/a5CV40000000TmnMAE/t394301
Susan

 

[PRATHAP96]

Please show the CONFIG items and the rest of the code.
Is the ISR being called?
How is 'result' declared?
How are you determining that "...output is[sic] not occurred"?
Susan

I have attach my configuration of the code. please check and let me help.

void SCCP1_InputCapture_Initialize(void)
{
    // MOD Every rising edge; CCSEL enabled; TMR32 16 Bit; TMRPS 1:1; CLKSEL FOSC/2; TMRSYNC disabled; CCPSLP disabled; CCPSIDL disabled; CCPON disabled;
    CCP1CON1L = 0x11; //The module is disabled, till other settings are configured.
    //SYNC CLC1; ALTSYNC disabled; ONESHOT disabled; TRIGEN disabled; IOPS Each Time Base Period Match; RTRGEN disabled; OPSRC Timer Interrupt Event;
    CCP1CON1H = 0x10;
    //ASDG 0x0; SSDG disabled; ASDGM disabled; PWMRSEN disabled;
    CCP1CON2L = 0x0;
    //ICSEL None; AUXOUT Disabled; ICGSM Level-Sensitive mode; OCAEN disabled; OENSYNC disabled;
    CCP1CON2H = 0x0;
    //PSSACE Tri-state; POLACE disabled; OSCNT None; OETRIG disabled;
    CCP1CON3H = 0x0;
    //ICOV disabled; ICDIS disabled; SCEVT disabled; ASEVT disabled; TRCLR disabled; TRSET disabled; ICGARM disabled;
    CCP1STATL = 0x0;
    //TMRL 0x0000;
    CCP1TMRL = 0x0;
    //TMRH 0x0000;
    CCP1TMRH = 0x0;
    //PRL 0;
    CCP1PRL = 0x0;
    //PRH 0;
    CCP1PRH = 0x0;
    //CMPA 0;
    CCP1RA = 0x0;
    //CMPB 0;
    CCP1RB = 0x0;
    //BUFL 0x0000;
    CCP1BUFL = 0x0;
    //BUFH 0x0000;
    CCP1BUFH = 0x0;
   
    SCCP1_InputCapture_CallbackRegister(&SCCP1_InputCapture_Callback);

    IFS0bits.CCP1IF = 0;
    // Enabling SCCP1 interrupt
    IEC0bits.CCP1IE = 1;

    CCP1CON1Lbits.CCPON = 1; //Enable Module

}

1. sccp1 interrupt called in main function .
2. "Result" we are using extern.

 

[Aussie Susan]

No - that is the initialisation of the SCCP.
What I asked for is the CONFIG settings - they are often #pragma lines at the top of the main code file. It may well be that you have not configured the oscillator to run at all but we can't tell. Also the code for the main() function woudl help in this regard.
Also how 'result' is defined is critical but not shown. If it is updated in an ISR then it must be declared volatile.
You don't call an ISR - the hardware does that for you when the conditions you have requested are met - in your case OPS3 in CCP1CON1H is 0 so every edge.
Are you running in debug mode and setting breakpoints to see what is working and what is not?
Susan

 

[PRATHAP96]

I have attach my configuration of the code. please check and let me help.

void CLOCK_Initialize(void)
{
    /* 
       Input frequency                               :  8.00 MHz
       Clock source                                  :  FRC Oscillator
       System frequency (Fosc)                       :  8.00 MHz
       Clock switching enabled                       :  false
       Auxiliary clock source                        :  FRC Oscillator
       Auxiliary clock input frequency               :  8.00 MHz
       Auxiliary clock PLL output frequency (AFpllo) :  8.00 MHz
    */
    // RCDIV FRC/1; PLLPRE 1:1; DOZE 1:8; DOZEN disabled; ROI disabled;
    CLKDIV = 0x3001;
    // PLLDIV 150;
    PLLFBD = 0x96;
    // TUN Center frequency;
    OSCTUN = 0x0;
    // PLLPOST 1:4; VCODIV FVCO/4; POST2DIV 1:1;
    PLLDIV = 0x41;
    // ENAPLL disabled; FRCSEL FRC Oscillator; APLLPRE 1:1;
    ACLKCON1 = 0x101;
    // APLLFBDIV 150;
    APLLFBD1 = 0x96;
    // APSTSCLR 1:4; APOST2DIV 1:1; AVCODIV FVCO/4;
    APLLDIV1 = 0x41;
    // CANCLKEN disabled; CANCLKSEL FVCO/4; CANCLKDIV Divide by 1;
    CANCLKCON = 0x500;
    // ROEN disabled; DIVSWEN disabled; ROSLP disabled; ROSEL ; OE disabled; ROSIDL disabled;
    REFOCONL = 0x0;
    // RODIV 0;
    REFOCONH = 0x0;
    // ROTRIM 0;
    REFOTRIMH = 0x0;
    // IOLOCK disabled;
    RPCON = 0x0;
    // PMDLOCK disabled;
    PMDCON = 0x0;
    // ADC1MD enabled; T1MD enabled; U2MD enabled; U1MD enabled; SPI2MD enabled; SPI1MD enabled; QEIMD enabled; PWMMD enabled; I2C1MD enabled; C1MD enabled;
    PMD1 = 0x0;
    // CCP2MD enabled; CCP1MD enabled; CCP4MD enabled; CCP3MD enabled; CCP7MD enabled; CCP8MD enabled; CCP5MD enabled; CCP6MD enabled; CCP9MD enabled;
    PMD2 = 0x0;
    // U3MD enabled; CRCMD enabled; I2C2MD enabled; I2C3MD enabled; QEI2MD enabled;
    PMD3 = 0x0;
    // REFOMD enabled;
    PMD4 = 0x0;
    // DMA1MD enabled; DMA2MD enabled; DMA3MD enabled; DMA0MD enabled; SPI3MD enabled;
    PMD6 = 0x0;
    // PTGMD enabled; CMP1MD enabled; CMP3MD enabled; CMP2MD enabled;
    PMD7 = 0x0;
    // DMTMD enabled; CLC3MD enabled; OPAMPMD enabled; BIASMD enabled; CLC4MD enabled; SENT1MD enabled; CLC1MD enabled; CLC2MD enabled; SENT2MD enabled;
    PMD8 = 0x0;
    // CF no clock failure; NOSC FRC; CLKLOCK unlocked; OSWEN Switch is Complete;
    __builtin_write_OSCCONH((uint8_t) (0x00));
    __builtin_write_OSCCONL((uint8_t) (0x00));
}

bool CLOCK_AuxPllLockStatusGet(void)
{
    return ACLKCON1bits.APLLCK;
}

 

[Aussie Susan]

Again, that is not what I asked for. Please re-read my previous posts carefully.
That looks like MCC generated code (almost all of it is unnecessary but that is MCC all over) but whether it is actually doing anything relies entirely on how you have set up the FOSCSEL config register that will be configured by the #pragma line. Given that you are using FOSC for the main code, you can set the FNOSC bits to FRC and forget this part entirely.
Of course, none of this answers your question and until you provide the information requested, I can't help you further.
Susan