[SOLVED] dsPIC30F2020, problem with calculation of sampling rate of ADC

[maxwell_30]

can somebody please tell me how microchip calculates the maximum sampling rate of the ADC of dspic30f2020 to be 2 mega samples/sec ? I tried going through the datasheet but was unable to figure it out :/

 

[Aussie Susan]

See Section 31.4 of the FRM document for the device that covers the ADC as it explains the process.
Basically the fastest clock you can use is 60MHz. A single channel requires 12 clocks (Tad) made up of 2 Tad for the sampling and 10 for the conversion. As the channels are always sampled in pairs, that takes 24 Tad.
Assuming you can set up the peripheral so that 1 Tad equals 1 clock pulse, that means the maximum sampling rate is 60MHz/24 or 2.5MSPS.
I would assume that there is some overhead so they state 2MSPS.
Susan

 

[maxwell_30]

thanks susan, I get it now. But i have one more doubt, in the data sheet, in many places its written that the controller works at 30 MIPS when an external oscillator of 15 Mhz is used and PLL is enabled. Now i am assuming that this 30 MIPS comes from the instruction clock frequency i.e. Fcy (15*32/(8*2)=30 MHz). But, not all instructions take only one clock cycle. So how can they say that the controller works at 30 million instructions per second?

 

[Aussie Susan]

I can't answer on behalf of the Microchip Marketing, but if you look at the instruction timing summary, you will see that the majority of instructions take one cycle. The ones that take 2 (or even 3) cycles are those that involve branching and the call/return/interrupt handling ones. (Of course the division' instructions are the exceptions by taking 18 clocks!).
I am guessing that, given a 'typical' mix of instructions that are actually executed by the CPU, they average out to something only a bit over 1 cycle.
Susan

 

[bigdogguru]

I thought I should also point out, not all dsPIC30F2020s are created equal.

The Extend Range devices, dsPIC30F2020-20E, can operate with a maximum system clock (Fcy) of 40MHz with a corresponding instruction clock (Tcy) of 20MHz or 20MIPS, within an extended temperature range of -40C to +125C.

The Industrial Range devices, dsPIC30F2020-30I, can operate with a maximum system clock (Fcy) of 60MHz with a corresponding instruction clock (Tcy) of 30MHz or 30MIPS, within an industrial temperature range of -40C to +85C.

Reference: dsPIC30F1010/202X Datasheet, Section: 21.1 DC Characteristics, Page: 231




Also both versions of the dsPIC30F2020 offers high speed internal RC oscillator, 14.55 MHz (±1%) for the Industrial Temp Range devices and 9.7 MHz (±1%) Extended Temp Range devices, which can be utilized in conjunction with the PLL to obtain Tcy close to 30MHz and 20MHz respectfully.


BigDog

 

[bigdogguru]

can somebody please tell me how microchip calculates the maximum sampling rate of the ADC of dspic30f2020 to be 2 mega samples/sec ? I tried going through the datasheet but was unable to figure it out :/

I was examining the Errata for the dsPIC30F2020 and thought you might find the following of interest:

Reference: dsPIC30F1010/202X Family Silicon Errata and Data Sheet Clarification, Section: 11 Module: ADC, Page: 8

11. Module: ADC
The data sheet indicates that the conversion rate
for the ADC module is 2.0 Msps. The ADC module
on the dsPIC30F1010/202X Rev. A3 silicon has a
maximum conversion rate of 1.5 Msps.

Work around
None.

Therefore, if you have the latest silicon revision, A3, the ADC is limited to 1.5Msps, not the 2Msps as advertised.


BigDog