DSP algorithm for DAC input variation

[Maitry07]

Hello,
My digital data range is dynamic range is 0033 H to 1013 H. Now This digital data is going at the input of 16 bit DAC - 5754R having a output voltage range is 0 to 5 V. So, I change the scale of 0033 H to 1013 H to 0000 H to FFFF H. so that my DAC output range is 0 to 5 V for all 4 channels. My each individual DAC channel is being updated with 1 MSPS DAC interface update rate. so, one by one my each DAC channel is getting updated.

Now I wanted to add one more algorithm such as comparison algorithm that can compare the current 16 bit digital data for channel 1 with the previous 16 bit digital data and if both data are same or else if there are +/- 2 bit variation , then the comparison algorithm will not generate any new output and As DAC 5754R will hold the old output as far as there is no output generation from comparison algorithm and latch the output based on the same old data.

This comparison algorithm need to be added at the output of scaling algorithm . Could you suggest what could be the suitable method to implement comparison algorithm?

Awaited your response.

--- Updated Oct 22, 2024 ---

One more thing, As This comparison algorithm need to simultaneously compare the all 4 data input with the previous one for all 4 DAC channels and comparison algorithm need to provide only that specific new output for that specific channel which are being changed from the previous one.

 

[potdew]

Hello,
My digital data range is dynamic range is 0033 H to 1013 H. Now This digital data is going at the input of 16 bit DAC - 5754R having a output voltage range is 0 to 5 V. So, I change the scale of 0033 H to 1013 H to 0000 H to FFFF H. so that my DAC output range is 0 to 5 V for all 4 channels. My each individual DAC channel is being updated with 1 MSPS DAC interface update rate. so, one by one my each DAC channel is getting updated.

Now I wanted to add one more algorithm such as comparison algorithm that can compare the current 16 bit digital data for channel 1 with the previous 16 bit digital data and if both data are same or else if there are +/- 2 bit variation , then the comparison algorithm will not generate any new output and As DAC 5754R will hold the old output as far as there is no output generation from comparison algorithm and latch the output based on the same old data.

This comparison algorithm need to be added at the output of scaling algorithm . Could you suggest what could be the suitable method to implement comparison algorithm?

Awaited your response.

--- Updated Oct 22, 2024 ---

One more thing, As This comparison algorithm need to simultaneously compare the all 4 data input with the previous one for all 4 DAC channels and comparison algorithm need to provide only that specific new output for that specific channel which are being changed from the previous one.

For each channel, compare the current digital data with the previous data.
Use the following logic:
for (int channel = 0; channel < 4; channel++) {
// Assuming currentData is the new input array for the current values
int currentValue = currentData[channel];
int previousValue = previousData[channel];

// Compare values
if (currentValue != previousValue && (abs(currentValue - previousValue) > 2)) {
// New value is significant enough to update
outputData[channel] = currentValue; // Update output data for DAC
previousData[channel] = currentValue; // Update previous data
} else {
// No significant change, hold old output
outputData[channel] = previousValue; // Maintain old output
}
}

 

[barkerxavierr]

Hello! I would like to consult the method!

 

[KlausST]

Hi,

I personally don´t see much benefit in this algorithm.

I mean: The interface and the controller needs to be fast enough to feed all DACs at full speed.
Even with this algorithm .. there should be a fairly high chance that there are times when all 4 DACs need to be updated (because all values change that much).
Then ... it has to work. And the interface need to be able to handle it.

--> So, what is the benefit?

the current 16 bit digital data for channel 1 with the previous 16 bit digital data and if both data are same or else if there are +/- 2 bit variation

This will never be the case. Since you scale the input date with a multiplier with a factor of more than 16. Thus the smallest step size will be 16 or 17 (depending on input data).
A +/- 2 LSB step size in the 16 bit value is impossible.
****

Even if you use the full 16 bit range (no missing codes) .. then a +/-2LSB minimum step size degrades overall performance almost down to a 14 bit DAC.
(for sure the multiply by 16 also reduces the performance almost down to 12 bit DAC)

Klaus

 

[danadakk]

Sure sounds like a CPLD with a state machine, and DMA functionality to
handle this in HW.