#include <mega128a.h>
#include <spi.h>
#include <delay.h>
#include <stdio.h>
#define CDSCLK1 PORTE.3
#define CDSCLK2 PORTE.4
#define ADCCLK PORTE.5
#define DELAY_NS(x)
int Flag;
int k;
int i;
float a[100];
// Declare your global variables here
#ifndef RXB8
#define RXB8 1
#endif
#ifndef TXB8
#define TXB8 0
#endif
#ifndef UPE
#define UPE 2
#endif
#ifndef DOR
#define DOR 3
#endif
#ifndef FE
#define FE 4
#endif
#ifndef UDRE
#define UDRE 5
#endif
#ifndef RXC
#define RXC 7
#endif
#define FRAMING_ERROR (1<<FE)
#define PARITY_ERROR (1<<UPE)
#define DATA_OVERRUN (1<<DOR)
#define DATA_REGISTER_EMPTY (1<<UDRE)
#define RX_COMPLETE (1<<RXC)
// USART1 Receiver buffer
#define RX_BUFFER_SIZE1 8
char rx_buffer1[RX_BUFFER_SIZE1];
#if RX_BUFFER_SIZE1 <= 256
unsigned char rx_wr_index1,rx_rd_index1,rx_counter1;
#else
unsigned int rx_wr_index1,rx_rd_index1,rx_counter1;
#endif
// This flag is set on USART1 Receiver buffer overflow
bit rx_buffer_overflow1;
// USART1 Receiver interrupt service routine
interrupt [USART1_RXC] void usart1_rx_isr(void)
{
char status,data;
status=UCSR1A;
data=UDR1;
if (data=='u')
{
}
if ((status & (FRAMING_ERROR | PARITY_ERROR | DATA_OVERRUN))==0)
{
rx_buffer1[rx_wr_index1++]=data;
#if RX_BUFFER_SIZE1 == 256
// special case for receiver buffer size=256
if (++rx_counter1 == 0)
{
#else
if (rx_wr_index1 == RX_BUFFER_SIZE1) rx_wr_index1=0;
if (++rx_counter1 == RX_BUFFER_SIZE1)
{
rx_counter1=0;
#endif
rx_buffer_overflow1=1;
}
}
}
// Get a character from the USART1 Receiver buffer
#pragma used+
char getchar1(void)
{
char data;
while (rx_counter1==0);
data=rx_buffer1[rx_rd_index1++];
#if RX_BUFFER_SIZE1 != 256
if (rx_rd_index1 == RX_BUFFER_SIZE1) rx_rd_index1=0;
#endif
#asm("cli")
--rx_counter1;
#asm("sei")
return data;
}
#pragma used-
// Write a character to the USART1 Transmitter
#pragma used+
void putchar1(char c)
{
while ((UCSR1A & DATA_REGISTER_EMPTY)==0);
UDR1=c;
}
#pragma used-
void Desiable (void)
{
// SPI initialization
// SPI Type: Master
// SPI Clock Rate: 125.000 kHz
// SPI Clock Phase: Cycle Start
// SPI Clock Polarity: Low
// SPI Data Order: MSB First
SPCR=0x52;
SPSR=0x00;
PORTB.0=0 ; //Congiguration Bit
spi(0x00);
//delay_us(1);
spi(0x0F);
PORTB.0=1 ;
PORTB.0=0 ; //Mux bit
spi(0x10);
//delay_us(1);
spi(0x08);
PORTB.0=1 ;
}
void Enable (void)
{
// SPI initialization
// SPI Type: Master
// SPI Clock Rate: 125.000 kHz
// SPI Clock Phase: Cycle Start
// SPI Clock Polarity: Low
// SPI Data Order: MSB First
SPCR=0x52;
SPSR=0x00;
PORTB.0=0 ; //Congiguration Bit
spi(0x00);
//delay_us(1);
spi(0x0E);
PORTB.0=1 ;
PORTB.0=0 ; //Mux bit
spi(0x10);
//delay_us(1);
spi(0x08);
PORTB.0=1 ;
PORTB.0=0 ; //Gain A bit
spi(0x20);
// delay_us(1);
spi(0x3f);
PORTB.0=1 ;
}
void main(void)
{
Flag=1;
//unsigned int x;
//unsigned char a;
// Port B initialization
// Func7=In Func6=In Func5=In Func4=In Func3=In Func2=Out Func1=Out Func0=Out
// State7=T State6=T State5=T State4=T State3=T State2=0 State1=0 State0=0
PORTB=0x00;
DDRB=0x07; // Set MOSI and SCK and SS output, all others input
PORTE=0x00;
DDRE=0x38; //Set CDSCLK1, CDSCLK2 and ADCCLK as output
PORTF=0xff;
DDRF=0x00;
// USART1 initialization
// Communication Parameters: 8 Data, 1 Stop, No Parity
// USART1 Receiver: On
// USART1 Transmitter: On
// USART1 Mode: Asynchronous
// USART1 Baud Rate: 9600
UCSR1A=0x00;
UCSR1B=0x18;
UCSR1C=0x06;
UBRR1H=0x00;
UBRR1L=0x33;
while (Flag==1)
{
for (i=0; i<100; i++)
{
CDSCLK2 =0;
ADCCLK=1;
DELAY_NS(10);
ADCCLK=0;
Enable();
DELAY_NS(8);
CDSCLK2 =1;
DELAY_NS(2);
ADCCLK=1;
a[i]=PINF;
DELAY_NS(2);
CDSCLK2 =0;
DELAY_NS(8);
ADCCLK=0;
a[i+1]=PINF;
Desiable();
}
for(k=0; k<100;k++)
{
putchar1(a[k]);
delay_ms(1);
}
Flag=0;
}
}