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[SOLVED] driving a signal by the procedure in vhdl

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hpb

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hi all;
I want to write a procedure for controlling the output to a serial data transmitter(This is my requirement).
Is it possible to drive a signal from a procedure?
waiting for your answers....
 

Yes. Im guessing there are more questions?
 

But i`m getting the error like "Cannot drive signal "hdr_wrt" from procedure "send_tx_data"." in modelsim_altera.....
 

well post some code so we can have a look.
 

A portion of the code

---------------------------------------------------------------------------------
-- Procedure SEND_TX_DATA --
---------------------------------------------------------------------------------
procedure SEND_TX_DATA (
no_of_packets :in integer;
error_flag0 :in std_logic;
error_flag1 :in std_logic;

) is
variable packet_cnt : integer;
variable enb : std_logic;
begin
packet_cnt := no_of_packets;
if(dclk'event and dclk = '1') then

if (error_flag0 = '1') then -- Send only the data bits
while (packet_cnt = 0) loop
for k in 0 to 1023 loop
rand_en <= '1';
end loop;
rand_en <= '0';
packet_cnt := packet_cnt-1;
end loop;

elsif (error_flag1 = '1') then
while (packet_cnt = 0) loop
-- Send the header
for j in 0 to 31 loop
rand_data_s <= header_data(j);
-- Write the header
if (j = 31) then
hdr_wrt <= '1';
end if;
end loop;
for k in 0 to 983 loop -- Send the Data of 123bytes
rand_en <= '1';
end loop;
rand_en <= '0';
packet_cnt := packet_cnt-1;
end loop;


end if;
end if;
end SEND_TX_DATA;

-----------------------------------------------------------------------------------------------
errors are
# -- Compiling architecture behav of serial_in_intf
# ** Error: D:/iwave/HP/ser_data_rec/iW-EMDRV-SI-01-R1.0-REL1.2-FPGA/Interfaces/serial_in_intf.vhd(76): Cannot drive signal "rand_en" from procedure "send_tx_data".
# ** Error: D:/iwave/HP/ser_data_rec/iW-EMDRV-SI-01-R1.0-REL1.2-FPGA/Interfaces/serial_in_intf.vhd(78): Cannot drive signal "rand_en" from procedure "send_tx_data".
# ** Error: D:/iwave/HP/ser_data_rec/iW-EMDRV-SI-01-R1.0-REL1.2-FPGA/Interfaces/serial_in_intf.vhd(86): Cannot drive signal "rand_data_s" from procedure "send_tx_data".
# ** Error: D:/iwave/HP/ser_data_rec/iW-EMDRV-SI-01-R1.0-REL1.2-FPGA/Interfaces/serial_in_intf.vhd(266): VHDL Compiler exiting
 
Last edited:

wow - thats a large procedure. Why are you using a procedure, and not a process?

I assume you realise this procedure probably isnt doing what you expect it to do. Loops are unrolled into parrallel hardware, plus also files are not synthesisable - so I assume this is testbench code for simulation only?

There is a lot of code missing - where are you calling the procedure? is this procedure in a package? if its in a package, then you are missing a lot of signals on the input/output part, unless you also put the signals in a package - which is really bad form.
 

yes this is for testbench implementation ......
But the main problem it`s giving that the signals declared in the architecture cannot be driven by this procedure....
 

yes they can - we need to see how you are calling the procedure.

I suggest posting all of the code (and please use syntax tags).
 

this is the architecture containing the procedure
architecture behav of serial_in_intf is
-
procedure SEND_TX_DATA (
no_of_packets :in integer;
error_flag0 :in std_logic;
error_flag1 :in std_logic;
) is
variable packet_cnt : integer;
variable enb : std_logic;
begin
packet_cnt := no_of_packets;
if(dclk'event and dclk = '1') then

if (error_flag0 = '1') then -- Send only the data bits
while (packet_cnt = 0) loop
for k in 0 to 1023 loop
rand_en <= '1';
end loop;
rand_en <= '0';
packet_cnt := packet_cnt-1;
end loop;

else (error_flag1 = '1') then
while (packet_cnt = 0) loop
-- Send the header
for j in 0 to 31 loop
rand_data_s <= header_data(j);
-- Write the header
if (j = 31) then
hdr_wrt <= '1';
end if;
end loop;
for k in 0 to 983 loop -- Send the Data of 123bytes
rand_en <= '1';
end loop;
rand_en <= '0';
packet_cnt := packet_cnt-1;
end loop;



end if;
end if;
end SEND_TX_DATA;


end behav;
-----------------------------------------------------------
then calling it`s simple like
------------------------------------------------------------
process
begin
if (reset = '1') then
case test_no is
when 1 => SEND_TX_DATA (100, '0', '0', '0', '0');
wait for 100 ms;
 
Last edited:

This isnt the whole code - please post the file.
I also notice all of these loops - you realise they will all complete within 1 clock cycle - because you have no waits inside the procedure, so things like rand_en will just stay at '0' because you set it to '0' last as the procedure completes.

- - - Updated - - -

Plus, as this is a testbench, did you know VHDL has a built in random number generator?
 

ok...lets make the question simpler...
i wrote a simple procedure package as shown below.....

library ieee,std;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use std.textio.all ;
use ieee.std_logic_textio.all ;
use work.all;
package my_package1 is
procedure writeTofile ( text_string: in std_logic_vector ( 15 downto 0));

end my_package1;

package body my_package1 is

procedure writeTofile ( text_string: in std_logic_vector ( 15 downto 0)) is
variable L : line;
begin
hwrite (L, text_string);
writeline (tx_serial_in, L);

end writeTofile;

end my_package1;
while compiling i get an error
# ** Error: D:/iwave/HP/ser_data_rec/iW-EMDRV-SI-01-R1.0-REL1.2-FPGA/my_package1.vhd(20): (vcom-1136) Unknown identifier "tx_serial_in".
 

whether you're using a package or not, it doesn't matter.
tx_serial_in is not defined within the procedure writeTofile (it starts with the keyword 'procedure' and ends with the keyword 'end'), so yes, the error message is correct "Unknown identifier".

And pls use the syntax or code tags.
 

removed due to unnecessary statements.....
 

whether you're using a package or not, it doesn't matter.
tx_serial_in is not defined within the procedure writeTofile (it starts with the keyword 'procedure' and ends with the keyword 'end'), so yes, the error message is correct "Unknown identifier".

And pls use the syntax or code tags.

I think you mean it's not defined within the scope of the procedure. Procedures can read and modify external signals and variables as long as they are within scope of the procedure.
 

I think you mean it's not defined within the scope of the procedure. Procedures can read and modify external signals and variables as long as they are within scope of the procedure.

i`m new to vhdl, so i`m asking what do u mean by scope of the procedure?
 

its basically the same as scope in any language:

consider this code:


Code VHDL - [expand]
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procedure do_something is
  variable a,b  : integer;
  constant C    : integer := 10;
  
  procedure do_something_else is
    variable a,d : integer;
  begin
    d := 10;
    a := C + d; --uses local version of a because it has the narrower scope, answer is 20;    
    b := a;  --can see b because it is declared above this procedure.
  end procedure;
  
begin
  
  do_something_else;
  --b now 20
  
  b := b + C;    
  --b is now 30
  
  d := C; --illegal, because there is no d in scope - it is only contained inside the do_something_else procedure;
  
end procedure;

 
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    hpb

    Points: 2
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thank u all;
I found the solution for my problem. I included my procedure block inside a process block. Now it`s working fine without even any warnings... thank you for sharing your knowledge with me... I have learnt a lot off things from you.... thank you.....
 

Yes - procedures procedures have to be called inside processes. I hope you've modified your procedure, because I know it will not work at all the way you think its going to work.
 

Yes - procedures procedures have to be called inside processes. I hope you've modified your procedure, because I know it will not work at all the way you think its going to work.

Yes, I`ve modified....
Thanks to ur patience to understand and answer my questions....
 

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