[SOLVED] Driving a DDR3 using MIG-7

[aminpix]

Hi
I am using Vivado 2015.1 and I try to use a DDR3 RAM, connected to the Artix-7. I have two input clocks, 25 Mhz and 27 Mhz.

Any body can help me to assign proper frequencies for system clock and reference clock.
I tried to use internal PLL of the FPGA, but somebody told me in MIG the input clock must be external and I can not use PLL.

 

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The MIG design contains the MMCM/PLL for the clocks required for the controller. The 25 and 27 MHz are not allowed as input clocks for the DDR 3 controller wizard (100 MHz is the lowest). I suspect you will have worse jitter performance with the 25 MHz than with a 100 MHz, which will reduce you're margins with an 800 MHz DDR3 design.

If you insist on using the 25 MHz then you need to modify the MMCM/PLL cores that are in the DDR3 controller and regenerate them using the 25 MHz input clock instead of the default value of something like 100/200 MHz. Look at the mig_7serires_v2_2_infrastructure.v file produced in the ddr3.srcs\sources_1\ip\mig_7series_0\mig_7series_0\user_design\rtl\clocking directory.

You could also cascade the PLL and the DDR3 controller MMCM/PLL which isn't optimal for jitter.

 

[aminpix]

If I use the internal PLL of the FPGA (I assume Clock Wizard), what should I do? Should I generate 200 MHz and connect to the system clock?

 

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Actually I just took a look at ug586 and there seems to be some stipulations on the allowed frequencies of the refclk and the sysclk, which you can't violate, which means that you probably can't use 25 MHz to generate a internal refclk and sysclk, as it states that the input clock has to be from a CCIO pin in the DDR3 bank.

 

[aminpix]

You are right, we can not use the IP and drive the DDR3 with 25 MHz, I changed the IP. It was a huge project but now I can use it.
Thank you very much.