DRC VDB problem while configuring the new 65nM library

[vinu2086]

1. We have Configured the 65NM UMC library successfully and able to run schematic level simulation in spectre.
2. I have converted the schematic into the layout . During this time MOS Transistors are displayed with a cross-mark(see the attachement).
3. Then when i try for DRC run, DRC VDB Error message is occuring ....

In the CIW window,error shown as 1304. Illegal Input Layer for whole page

Tried configuring , but fails....

Can some of my seniors help me to resolve the same ? Thanks in advance

Note: Initially this error was there for *.rul file path issue. When i resolved that, this new DRC VDB error is coming.....Also, for 180NM UMC technology file DRC is working fine.

 

[nikhilquick]

1. We have Configured the 65NM UMC library successfully and able to run schematic level simulation in spectre.
2. I have converted the schematic into the layout . During this time MOS Transistors are displayed with a cross-mark(see the attachement).
3. Then when i try for DRC run, DRC VDB Error message is occuring ....

In the CIW window,error shown as 1304. Illegal Input Layer for whole page

Tried configuring , but fails....

Can some of my seniors help me to resolve the same ? Thanks in advance

Note: Initially this error was there for *.rul file path issue. When i resolved that, this new DRC VDB error is coming.....Also, for 180NM UMC technology file DRC is working fine.

Please tell me what changes have to be made in rule file of UMC180 for DRC............... urgent

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Please tell me what changes have to be made in rule file of UMC180 for DRC............... urgent