pokemonstation
Junior Member level 1
ibm what is drc index
Hello,
I have a general question about DRC.
I was using Synopsys Hercules to run DRC on a simple inverter circuit built with 65nm IBM PDK (cmos10lpe) and I got some errors. Then I decided to erase everything and instantiate a single cell (nfet) and run DRC on it. To my surprise, I still get many of the same errors, which is really strange since I instantiated an IBM PDK cell.
Is this normal? I just couldn't imagine that foundry would provide PDk cells that can't even pass its own DRC rules. The rule set or runset I used is included in the PDK. Some DRC errors on a single nfet cell are ridiculous for 65nm technology, such as "length must be greater than 3.0um" and "area must be greater than 1.12um^2).
I also have a quick question about layout. In the LSW window, some items are labeled as "drw" and some are "dg". I have only used "drw" before. Can anyone please tell me what does item with "dg" label in the LSW window do?
Many thanks in advance
Michael
Hello,
I have a general question about DRC.
I was using Synopsys Hercules to run DRC on a simple inverter circuit built with 65nm IBM PDK (cmos10lpe) and I got some errors. Then I decided to erase everything and instantiate a single cell (nfet) and run DRC on it. To my surprise, I still get many of the same errors, which is really strange since I instantiated an IBM PDK cell.
Is this normal? I just couldn't imagine that foundry would provide PDk cells that can't even pass its own DRC rules. The rule set or runset I used is included in the PDK. Some DRC errors on a single nfet cell are ridiculous for 65nm technology, such as "length must be greater than 3.0um" and "area must be greater than 1.12um^2).
I also have a quick question about layout. In the LSW window, some items are labeled as "drw" and some are "dg". I have only used "drw" before. Can anyone please tell me what does item with "dg" label in the LSW window do?
Many thanks in advance
Michael
