DRC Error: PSUB_STAMPERRORMULT

[sumangalareddy]

Can u please tell how to remove DRC ERROR: PSUB_STAMPERRORMULT...
what does this error mean....

 

[D.A.(Tony)Stewart]

It means Design Rule Check DRC error on Psub

Another student corrected his own error like this..

Apparently, since I was not using the PMOS and NMOS from the gpdk180 lib, I shouldnt have used another via. I should've construtec the via inside the Nwell from the PMOS, instead of creating another via with a new Nwell or using a via M1_Nwell

 

[erikl]

Seems you didn't connect all PSUB connections (p+ contacts of NMOS bulk in substrate) to the same potential node (by metal), usually to GND.

(Bulk connections get a STAMP, and if PSUB connections are not connected to the same potential, this means there are MULTiple potentials for these STAMP connections, which is not allowed for PSUB.)

I know this error message text PSUB_STAMPERRORMULT (and similar DRC error messages) aren't too helpful, and generations of layouters have asked for its meaning, but unfortunately the DRC rules' writers always persisted (and still do so) on such cryptic error messages, even in eras when message text lengths aren't a big issue any more.

 

[sumangalareddy]

thank u.... i Will check out...

for opamp layout psub is connected to vss i.e, -1v... for switch(2:1 MUX) psub is connected to gnd.... Is problem occuring due to this...??

 

[dick_freebird]

Probably. Like he said, only one potential for psub. Which should
be a well metallized supply terminal, most negative on the chip
(barring very special design measures and constrained device
subset).

 

[erikl]

... for opamp layout psub is connected to vss i.e, -1v... for switch(2:1 MUX) psub is connected to gnd.... Is problem occuring due to this...??

Probably. In vanilla CMOS processes you can't have negative bulk voltages (referred to GND). This would need a double/triple well or SOI process.

In bulk CMOS processes, Psub must be the most negative potential.