I am doing a asic semi-custom design. While doing a drc check in virtuoso, i put a exclude layer on the standard cell to avoid the tools to check the standard cell. This means im only checking the drc for interconnection between the standard cell. Eventually, i still have a errors after doing the drc check. The error is which is violated the rules are :
Via1 size = 0.26 * 0.26
Minimum MetalTop line width = 0.44um
All contacts must be covered with metal1
minimum poly overlap of contact > 0.10
minimum island overlap of contact > 0.10
Can anyone guide me on how to overcome this problem?
And another thing is, can anyone give the proper step to do a drc check.
could u please tell which DRC checks u are following i mean r using any other tool for DRC , if u r using mentors calibre . i can definately help u .there should not be much prob even if ur using Diva r Dracula rule files . so in any case let us know the procedure
Since you are using Diva rules file, there are actually not many options to check according to our needs. But there is one way to do so, you can go to the rules file and comment the rules which check VIA and others and then perform DRC, now the tool will ignore all the vias .