drc error :enclosure of chipedge

[guow06]

I am using tsmc90nm technology. I use calibre to do the DRC. There are errors like xx enclose from the chipedge < xx. I think it is because of the chipedge defined. How should I define the chipedge? or how should I define the area for DRC in calibre?
someone tells me i can define the area for drc in calibre, but how?

 

[skal81]

You should first check the options of your DRC deck. In TSMC data there is usually a variable to define the check area:
//#DEFINE ChipWindowUsed // Turn on to specify chip boundary directly by following variables
VARIABLE xLB 0.0 // x-coordinate of left-bottom corner for user defined chip window
VARIABLE yLB 0.0 // y-coordinate of left-bottom corner for user defined chip window
VARIABLE xRT 1000.0 // x-coordinate of right-top corner for user defined chip window
VARIABLE yRT 1000.0 // y-coordinate of right-top corner for user defined chip window

This variables are used to define the the total area.

If there is no such option try to see how the chipedge rules are defined.

 

[guow06]

Got it.
Thanks very much

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