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Do you want to take into account parasitic resistance of source / drain metallization? (this can contribute as much as 50% or more to the total Rdson, and can also create problems like current density / electromigration, uneven current distribution over device area or pads/balls, etc.).
If yes - you need to use a specialized software tool that is designed to handle these layouts properly (two-dimensional meshing of complex metal shapes, fracturing of gates along gate width, treating the device in truly distributed manner, etc.).
If not - you can can just use SPICE simulation for your power transistor, but you will get only device resistance part, and will not see any of the effects / problems mentioned above.